Add board from SCDZ with SOC from wch ch32v307 #90872

SoftwareArchitekt · 2025-05-30T14:33:45Z

Add a board from SCDZ named ch32v307evt
this board has a SOC from wch named ch32v307
inside SOC is a Qinke_v4f Core
There are some diffences to the wch-ch32v307 board, which I will add in the next step: Core Speed, LED, Switches

As it is my first PR for this project, forgive me if I had made mistakes

Is linkale, untested

github-actions · 2025-05-30T14:34:28Z

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nzmichaelh · 2025-06-01T08:12:31Z

Nice! Some starter comments: could you squash these commits so things like 'revert to the original main.c' go away, and use the Zephyr commit message style? I'll have a look at the contents now...

nzmichaelh · 2025-06-01T08:19:38Z

boards/scdz/ch32v307evt/doc/index.rst

@@ -0,0 +1,91 @@
+.. zephyr:board:: ch32v307evt


Do you have a link to the board (home page, store link, or similar) and schematic?

nzmichaelh · 2025-06-01T08:20:15Z

boards/scdz/ch32v307evt/doc/index.rst

+Overview
+********
+
+The `SCDZ`_ CH32V307EVT hardware provides support for QingKe 32-bit RISC-V4F


How attached are you to the 'evt' part of the name? I ask as WCH make a series that end with evt, but this board is by a different vendor.

@nzmichaelh yes, I have the 307-Board from wch here too. I use these name with endin evt here, because it is writen in this kind on the pcb. The wch-Board is named CH32V307V-R2-1v1 on the pcb. This (wch 307) I will do after this board is finished.

nzmichaelh · 2025-06-01T08:21:51Z

boards/scdz/ch32v307evt/doc/index.rst

+Overview
+********
+
+The `SCDZ`_ CH32V307EVT hardware provides support for QingKe 32-bit RISC-V4F


This looks like it was adapted from the other WCH READMEs. These were recently updated to fix some of the wording and style - could you pull in the same changes please?

nzmichaelh · 2025-06-01T08:23:21Z

dts/riscv/wch/ch32v307/ch32v307.dtsi

+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(32)>;


32 k or 64 k?

It's a bit complex, as it's possible to configure the amount of RAM you need (you can configure part of your ram to be a copy of the flash).

To change this configuration, you need to write some registers in sequence then reset. But, if I recall correctly, minichlink always write these bits so if you flash with minichlink you are kinda stuck in the state with 32 KB.

nzmichaelh · 2025-06-01T08:24:36Z

dts/riscv/wch/ch32v307/ch32v307.dtsi

+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(127)>;


127 or 120?

nzmichaelh · 2025-06-01T08:25:47Z

soc/wch/ch32v/qingke_v4f/qingke_v4_vector.S

+SECTION_FUNC(vectors, ivt)
+	.option norvc
+	/* Jump to 0x08000008, into the main flash zone where j __start is */
+	//lui	x5, 0x8000


Drop or uncomment the commented block

nzmichaelh · 2025-06-01T08:26:08Z

soc/wch/ch32v/qingke_v4f/qingke_v4_vector.S

+SECTION_FUNC(vectors, __start)
+	li 	a0, 0xf
+	csrw	mtvec, a0
+	j	__initialize


nit: add a blank line at the end of file

nzmichaelh · 2025-06-01T08:27:39Z

I see there are a few files that were renamed. Please drop those changes.

cfriedt

@SoftwareArchitekt - like Michael mentioned, git history needs to be cleaned up a bit.

Maybe

rebase this branch onto the latest main
reset back to main (leaving a number of staged changes
revert the changes that are unwanted / unneeded
Create a first commit for the soc changes
Create a second commit for the board changes

I think that should do it.

VynDragon · 2025-06-01T13:58:41Z

dts/riscv/wch/ch32v307/ch32v307.dtsi

@@ -0,0 +1,226 @@
+/*


Please add the packages on the model of the other SoCs

VynDragon · 2025-06-01T13:58:54Z

boards/scdz/ch32v307evt/ch32v307evt.dts

+
+/dts-v1/;
+
+#include <wch/ch32v307/ch32v307.dtsi>


Use package there.

Hi @VynDragon , I don't understand what you mean here. Could you please explain more detailed for me.

Look at this PR: #90992, it fixes the same issue

miggazElquez · 2025-06-03T09:36:05Z

dts/riscv/wch/ch32v307/ch32v307.dtsi

+				reg = <0x40010800 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;


ngpios should be 16 (for all the nodes)

nordicjm

squash commits

VynDragon · 2025-06-04T12:04:58Z

@SoftwareArchitekt https://git-scm.com/book/en/v2/Git-Tools-Rewriting-History, this commit history is not good for merging, you need to reorganize the whole PR.

sonarqubecloud · 2025-06-04T12:27:03Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

SoftwareArchitekt added 8 commits April 21, 2025 08:12

Add Board SCDZ CH32V307EVT with SOC wch_ch32v307

e9056c8

Is linkale, untested

fprintk and led runs

f565ea0

original main.c

4c38e96

fix gpio

7aeb128

Merge branch 'SCDZ_CH32V307EVT_Adding_Board_etc'

5a876a2

remove deleted file ch32fun.h

a50bb4e

remove not needed file and add soc

eef06df

Merge branch 'main' of https://github.com/zephyrproject-rtos/zephyr

6b7603f

github-actions bot added platform: WinChipHead area: Samples area: RISCV area: Debugging labels May 30, 2025

github-actions bot requested review from carlocaione, dcpleung, edersondisouza, fkokosinski, kartben, katsuster, kgugala, mgielda, mrkhldn, nashif, npitre, nzmichaelh, tgorochowik, VynDragon and ycsin May 30, 2025 14:34

github-actions bot assigned nashif May 30, 2025

Return to original main.c

701aaa7

SoftwareArchitekt added 2 commits May 31, 2025 13:45

return to riginal prj.conf

336f78b

back to original prj.conf without interrupt

497f6bd

nzmichaelh requested changes Jun 1, 2025

View reviewed changes

cfriedt reviewed Jun 1, 2025

View reviewed changes

VynDragon requested changes Jun 1, 2025

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miggazElquez reviewed Jun 3, 2025

View reviewed changes

SoftwareArchitekt added 2 commits June 3, 2025 14:55

Update ch32v307.dtsi number of gpios from 8 to 16

f2580f8

Merge branch 'zephyrproject-rtos:main' into main

23d7fec

nordicjm reviewed Jun 4, 2025

View reviewed changes

Merge branch 'zephyrproject-rtos:main' into main

0bfc1f9


		/dts-v1/;

		#include <wch/ch32v307/ch32v307.dtsi>

Add board from SCDZ with SOC from wch ch32v307 #90872

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Add board from SCDZ with SOC from wch ch32v307 #90872

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nzmichaelh commented Jun 1, 2025

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VynDragon commented Jun 4, 2025

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sonarqubecloud bot commented Jun 4, 2025

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