x64: Migrate some blend-related instructions #10975
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This commit migrates the `pblendvb`, `blendvps`, `blendvpd`, and AVX versions of each to the new assembler. This required a few minor features in the assembler: * The fixed physical `xmm0` register is now a `Location` * The "/is4" encoding format for VEX instructions is supported * The `Fixed` type now supports both xmm and gpr registers (minor update to its `to_string` method). In the end this enables deleting `XmmRmRBlend` and `XmmRmRBlendVex`. (yay!)
alexcrichton
commented
Jun 7, 2025
| ; pblendvb %xmm1, %xmm7, %xmm1 | ||
| ; pblendvb %xmm0, %xmm7, %xmm1 |
There was a problem hiding this comment.
I'll note that there's no actual register allocation changes here, this is just an artifact of how the instruction used to be printed. The xmm0 argument was omitted by default and the src/destination, which are required to be the same register, were printed twice.
github-actions
bot
added
cranelift
abrown
reviewed
Jun 9, 2025
| @@ -36,5 +36,12 @@ pub fn list() -> Vec<Inst> { | |||
|
|
|||
| inst("movddup", fmt("A", [w(xmm1), r(xmm_m64)]), rex([0xF2, 0x0F, 0x12]).r(), _64b | compat | sse3), | |||
| inst("vmovddup", fmt("A", [w(xmm1), r(xmm_m64)]), vex(L128)._f2()._0f().op(0x12).r(), _64b | compat | avx), | |||
|
|
|||
| inst("pblendvb", fmt("RM", [rw(xmm1), r(align(xmm_m128)), r(xmm0)]), rex([0x66, 0x0F, 0x38, 0x10]).r(), _64b | compat | sse41), | |||
There was a problem hiding this comment.
Suggested change
| inst("pblendvb", fmt("RM", [rw(xmm1), r(align(xmm_m128)), r(xmm0)]), rex([0x66, 0x0F, 0x38, 0x10]).r(), _64b | compat | sse41), | |
| inst("pblendvb", fmt("RM", [rw(xmm1), r(align(xmm_m128)), r(implicit(xmm0))]), rex([0x66, 0x0F, 0x38, 0x10]).r(), _64b | compat | sse41), |
Don't we want this to be implicit?
There was a problem hiding this comment.
I originally thought so yeah but apparently Capstone disassembles this with %xmm0 show it shows up in the instruction listing. It looks like even Intel-style disassembly shows xmm0 as well, so for whatever reason while it's implicit on instructions like div it's not implicit here...
abrown
approved these changes
Jun 9, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This commit migrates the
pblendvb,blendvps,blendvpd, and AVX versions of each to the new assembler. This required a few minor features in the assembler:xmm0register is now aLocationFixedtype now supports both xmm and gpr registers (minor update to itsto_stringmethod).In the end this enables deleting
XmmRmRBlendandXmmRmRBlendVex. (yay!)