A High-performance Timing Analysis Tool for VLSI Systems

A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

A Standalone Structural Verilog Parser

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

VLSI EDA Global Router

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

ASIC implementation flow infrastructure

RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).

design and verification of asynchronous circuits

A standalone structural (gate-level) verilog parser

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Awesome machine learning for logic synthesis

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"