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cpu: aarch64: prefer brgemm over jit for 1x1 convolutions with sve_256 #3411

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Merged
merged 1 commit into from
Jun 18, 2025

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Anallear
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@Anallear Anallear commented Jun 10, 2025

Description

Moving brgemm_1x1_convolution_fwd_t<sve_256> before the jit_sve_1x1_convolution_fwd implementation based on benchmark results showing better performance.

Performance improvements

  • When running using pytorch its showing slower results with stride 1, thats why we put a condition to run brgemm 1X1 when stride is more or equal to 2
  • Performance Results (these results ran on 16 threads )
    mb: mini batch size , ic: input channels , S: Stride
    Brgconv,
    S=1, mb=64, ic=384 ,time= 21.25 ms
    S=2, mb=64, ic=384 ,time= 5.48 ms
    S=3, mb=64, ic=384 ,time= 2.57 ms

JIT_1X1,
S=1, mb=64, ic=384 ,time= 21.62 ms
S=2, mb=64, ic=384 ,time= 6.16 ms
S=3, mb=64, ic=384 ,time= 5.87 ms

Bug fixes

  • Fixes nightly regression failures

@Anallear Anallear requested review from a team as code owners June 10, 2025 14:07
@github-actions github-actions bot added platform:cpu-aarch64 Codeowner: @oneapi-src/onednn-cpu-aarch64 component:common labels Jun 10, 2025
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Thanks for this fix, just few minor formatting issues and looks like you need to run clang-format!

@@ -44,6 +44,7 @@ using namespace data_type;

template <cpu_isa_t isa>
status_t brgemm_1x1_convolution_fwd_t<isa>::pd_t::init(engine_t *engine) {

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remove

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remove

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remove

@Anallear Anallear force-pushed the fixreg branch 2 times, most recently from d5ee1d9 to d94617f Compare June 12, 2025 12:49
Moving brgemm_1x1_convolution_fwd_t<sve_256> before the jit_sve_1x1_convolution_fwd implementation based on benchmark results showing better performance.
@Sqvid Sqvid merged commit fd8d5eb into uxlfoundation:main Jun 18, 2025
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5 participants