[FIRRTL] [Bug Report] Comb Loop Detect not aware of bitcast + extract

[sequencer]

See this MLIR Module of FIRRTL, the output output_0 should connected from input_0 with %3 = firrtl.bitcast %io and firrtl.bits %3 7 to 0:

module {
  firrtl.circuit "TEST" {
    firrtl.module @TEST(in %input_0: !firrtl.uint<8>, out %output_0: !firrtl.uint<8>) attributes {convention = #firrtl<convention scalarized>, layers = [@verification]} {
      %io = firrtl.wire : !firrtl.bundle<input_0 flip: uint<8>, output_0: uint<8>>
      %probe = firrtl.wire : !firrtl.bundle<>
      %0 = firrtl.subfield %io[input_0] : !firrtl.bundle<input_0 flip: uint<8>, output_0: uint<8>>
      firrtl.connect %0, %input_0 : !firrtl.uint<8>
      %1 = firrtl.subfield %io[output_0] : !firrtl.bundle<input_0 flip: uint<8>, output_0: uint<8>>
      firrtl.connect %output_0, %1 : !firrtl.uint<8>
      %2 = firrtl.subfield %io[output_0] : !firrtl.bundle<input_0 flip: uint<8>, output_0: uint<8>>
      %3 = firrtl.bitcast %io : (!firrtl.bundle<input_0 flip: uint<8>, output_0: uint<8>>) -> !firrtl.uint<16>
      %4 = firrtl.bits %3 7 to 0 : (!firrtl.uint<16>) -> !firrtl.uint<8>
      %_GEN_0 = firrtl.node interesting_name %4 : !firrtl.uint<8>
      firrtl.connect %2, %_GEN_0 : !firrtl.uint<8>
    }
    firrtl.layer @verification bind {
    }
  }
}

However, combinational cycle in a FIRRTL module, sample path: TEST.{_GEN_0 <- ... <- io_output_0 <- _GEN_0}

The firrtl.bitcast is only designed for lowering to hw.bitcast, see here, so CheckCombLoops will detect this as a loop.
The simplest way of fixing this postpone the CheckCombLoops to HW, and don't execute it in FIRRTL Pass.

[unlsycn]

The problem is that io is a bundle with subfields that have different directions; we should likely add an assertion to forbid bitcasting bundles like this?
For this case, you should use firrtl.subfield to extract the field and then bitcast it.

[uenoku]

FIRRTL checkcombloops has never intended to perform bit-sensitive tracking. Also it shouldn't rely on canonicalization. HW pass might work but it will be also tricky to verify IR generated by Firtool pipeline as it also includes SV stuff unfortunately.