boards: nordic: add 'iron' board variant

This is needed for next generation Secure Domain firmware.

Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>

Author: hakonfam

boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk

@@ -2,9 +2,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF54H20DK
-	select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP
+	select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP || \
+				       BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON)
 	select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD
 	select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \
 				       BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP)
 	select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \
 				        BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP)
+	select SOC_NRF54H20_IRON if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON

boards/nordic/nrf54h20dk/board.yml

@@ -9,6 +9,8 @@ board:
       cpucluster: cpuppr
     - name: xip
       cpucluster: cpuflpr
+    - name: iron
+      cpucluster: cpuapp
   revision:
     format: major.minor.patch
     default: "0.9.0"

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54h20dk_nrf54h20_cpuapp.dts"
+
+/delete-node/&cpurad_rx_partitions;
+/delete-node/&cpuapp_rx_partitions;
+/delete-node/&cpusec_cpuapp_ipc;
+
+/* This is not yet an exhaustive memory map, and contain only a minimum required to boot
+ * the application core.
+ */
+
+&mram1x {
+	cpuapp_rx_partitions: cpuapp-rx-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuapp_slot0_partition: partition@2c000 {
+			reg = <0x2c000 DT_SIZE_K(480)>;
+		};
+
+		cpuppr_code_partition: partition@a4000 {
+			reg = <0xa4000 DT_SIZE_K(64)>;
+		};
+
+		cpuflpr_code_partition: partition@b4000 {
+			reg = <0xb4000 DT_SIZE_K(48)>;
+		};
+	};
+};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_0_9_0.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf54h20dk/nrf54h20/cpuapp/iron
+name: nRF54H20-DK-nRF54H20-Application (IRONside compatible) (revision 0.9.0)
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+sysbuild: true
+ram: 256
+flash: 480
+supported:
+  - adc
+  - can
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - usbd

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_defconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot be applied
+# as the (0x0 - 0x400) region is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
+CONFIG_NRF_REGTOOL_GENERATE_UICR=n

samples/drivers/watchdog/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+	status = "okay";
+};

scripts/west_commands/runners/nrf_common.py

@@ -361,8 +361,11 @@ def program_hex(self):
                 )
 
             if self.erase:
-                self.exec_op('erase', core='Application', kind='all')
-                self.exec_op('erase', core='Network', kind='all')
+                if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON'):
+                    self.exec_op('erase', kind='all')
+                else:
+                    self.exec_op('erase', core='Application', kind='all')
+                    self.exec_op('erase', core='Network', kind='all')
 
             # Manage SUIT artifacts.
             # This logic should be executed only once per build.

soc/nordic/nrf54h/Kconfig.soc

@@ -33,5 +33,10 @@ config SOC_NRF54H20_CPUFLPR
 	help
 	  nRF54H20 CPUFLPR
 
+config SOC_NRF54H20_IRON
+	bool
+	help
+	  Indicates that local domain firmware is compatible with Nordic IRONside SE.
+
 config SOC
 	default "nrf54h20" if SOC_NRF54H20

tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54h20dk_nrf54h20_common.dtsi"

tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf

@@ -0,0 +1,2 @@
+# Disable dcache
+CONFIG_DCACHE=n

tests/drivers/watchdog/wdt_basic_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.overlay

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt010 {
+	status = "okay";
+};