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onstable

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Commits on Jan 3, 2024

• Update copyright year

  erendn

  committed
  0a1de57

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Commits on Jan 29, 2023

• Update copyright year

  erendn

  committed
  e5fc25d

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Commits on Nov 30, 2022

• Add copyright check to code format test

  erendn

  committed
  96e5750

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Commits on Nov 27, 2022

• Use library imports globally

  erendn

  committed
  fccdc3c

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Commits on Aug 18, 2022

• Further fixes for new verilog naming convention

  bugraonal

  committed
  25cc08d

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Commits on Jul 28, 2022

• Fixed write_size checks for None

  bugraonal

  committed
  a361d9f

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• Multibank file generation (messy)

  bugraonal

  committed
  c1e891b

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• modified template engine & sram multibank class

  bugraonal

  committed
  846dfc7

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• Template section clone method

  bugraonal

  committed
  bde4a38

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• TEmplate rework

  bugraonal

  committed
  9158e92

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• Base-verilog

  bugraonal

  committed
  a5728cd

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• Replaced instances of addr_size with bank_addr

  bugraonal

  committed
  30f5638

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• Multibank file generation (messy)

  bugraonal

  committed
  24bb6f8

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Commits on Jul 21, 2022

• modified template engine & sram multibank class

  bugraonal

  committed
  6d6063e

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• Template section clone method

  bugraonal

  committed
  b75e1fc

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• TEmplate rework

  bugraonal

  committed
  f2cd611

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• Base-verilog

  bugraonal

  committed
  988399b

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Commits on Oct 13, 2021

• Move mem reg before usage for compatibility

  mguthaus

  committed
  e6a0093

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Commits on Aug 28, 2021

• Fix write masks in Verilog

  erendn

  committed
  e9b370b

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Commits on Jul 30, 2021

• Fix addr flop in Verilog

  erendn

  committed
  85955ce

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Commits on Jun 21, 2021

• Fix error in 1 spare column Verilog

  mguthaus

  committed
  af31027

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Commits on Jun 18, 2021

• Fix error in no spare column verilog

  mguthaus

  committed
  6787717

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• Add spare cols to behavioral Verilog model

  mguthaus

  committed
  81d20ec

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Commits on May 26, 2021

• Update lib file with external supply names

  mguthaus

  committed
  e16f44c

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• Fix external supply names in verilog

  mguthaus

  committed
  d579a60

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Commits on May 6, 2021

• Fix Verilog module typo. Adjust RBL route.

  mguthaus

  committed
  e995e61

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Commits on Apr 30, 2021

• Add conditional power pins to Verilog model.

  mguthaus

  committed
  98fb34c

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Commits on Apr 15, 2021

• Merge remote-tracking branch 'olofk/verilog_model_features' into dev

  mguthaus

  committed
  aa5e1fd

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• Add HOLD_DELAY parameter for dout in verilog model

  Show description for 688a1f1
  olofk

  committed
  688a1f1

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• Add VERBOSE parameter to generated verilog model

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  olofk

  committed
  1d657ab

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Commits on Jan 22, 2021

• Update copyright year.

  mguthaus

  committed
  30fc81a

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Commits on Nov 18, 2020

• PEP8 cleanup

  mguthaus

  committed
  305b546

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• Remove partial Verilog output

  mguthaus

  committed
  02c1fac

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Commits on Nov 17, 2020

• Add custom cell custom port order code. Update setup/hold to use it.

  mguthaus

  committed
  baae281

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Commits on Nov 3, 2020

• Remove EOL whitespace globally

  mguthaus

  committed
  da721a6

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