This directory contains three sub-directories:
- core, where all of the actual components to the CPU proper are contained
- peripherals, where several common CPU peripherals are kept. These aren't really external peripherals per se, although they may be implemented as such. Rather, these peripherals are components that are important to the CPU's functionality. As such, they are often distributed with the CPU proper, and used internally by supervisor programs.
- ex, where some general wishbone cores are kept, such as arbiters, delays, and even where I keep a copy of the formal wishbone properties.
Within this ZipCPU RTL directory are four bus wrappers for the core of the ZipCPU. Two of these are Wishbone wrappers: ZipBones and ZipSystem. Another two are AXI-lite and AXI wrappers respectively: ZipAXIL and ZipAXI. These wrappers connect an external wishbone or AXI-lite slave interface to the debugging port of the CPU, so that the CPU can be reset, started, stopped, stepped, and in general debugged.
The ZipBones would be the appropriate wrapper if you want the CPU to fit in the tightest space possible (Ex: Digilent's CMod S6).
Use the ZipSystem if you want to couple some peripherals tightly to the CPU. These peripherals include:
- 2x Interrupt controllers
- Timers, and an experimental timer called zipjiffies that's been with the CPU for some time
- Performance counters, to measure your performance
- A Direct Memory Access Controller
- Or even the Memory Management Unit
Neither ZipBones, ZipAXIL, nor ZipAXI contain these peripherals. If you would like to use these peripherals with these wrappers, they'll need to be located external to the CPU and connected via your bus interconnect.
If you are just looking for the CPU's code itself, check out zipcore.v within the core subdirectory. That's of the main core of the ZipCPU itself.