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titaniumrgmii problem

Status: Open.

#2262 In enjoy-digital/litex;

· cicamargoba opened on Jun 17, 2025

ibex core building issue

Status: Open.

#2258 In enjoy-digital/litex;

· zaksalma02 opened on Jun 14, 2025

How to add gpio connected to user defined module in VHDL/Verilog?

Status: Open.

#2257 In enjoy-digital/litex;

· pratipm opened on Jun 14, 2025

How to contribute to LiteX Wiki?

Status: Open.

#2250 In enjoy-digital/litex;

· Rajnesh28 opened on May 30, 2025

Vivado: user constraints added as EARLY get overriden by Xilinx IP xdc

Status: Open.

#2245 In enjoy-digital/litex;

· enurseitov opened on May 14, 2025

NeoRV32: Issue with multiple CPU and Wishbone.

Status: Open.

#2229 In enjoy-digital/litex;

· enjoy-digital opened on Apr 24, 2025

Reception on the second UART does not work

Status: Open.

#2226 In enjoy-digital/litex;

· russo00 opened on Apr 13, 2025

Command litex_term is not working on Terasic De1-SoC FPGA.

Status: Open.

#2224 In enjoy-digital/litex;

· rohan23rao opened on Apr 10, 2025

issue when boot on tang-primer-20k with sdcard

answered-waiting-feedback

Status: Open.

#2217 In enjoy-digital/litex;

· yuKILLING opened on Mar 27, 2025

DE10-Lite memory error

Status: Open.

#2215 In enjoy-digital/litex;

· russo00 opened on Mar 24, 2025

C program Tang Primer 20K

Status: Open.

#2208 In enjoy-digital/litex;

· russo00 opened on Mar 14, 2025

SD-mode failing on LFE5U-25F boards

Status: Open.

#2201 In enjoy-digital/litex;

· machdyne opened on Mar 7, 2025