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[AArch64] Add FEAT_FPAC to Neoverse V2
This feature is supported in Grace, but wasn't specified in the CPU definition.
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4 files changed

+5
-2
lines changed

4 files changed

+5
-2
lines changed

Diff for: clang/test/Driver/aarch64-mcpu-native.c

+1
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
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// CHECK-FEAT-NV2: FEAT_FHM Enable FP16 FML instructions
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// CHECK-FEAT-NV2: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-FEAT-NV2: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-FEAT-NV2: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
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// CHECK-FEAT-NV2: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-FEAT-NV2: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-FEAT-NV2: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons

Diff for: clang/test/Driver/print-enabled-extensions/aarch64-grace.c

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@@ -19,6 +19,7 @@
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// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
@@ -59,4 +60,4 @@
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension

Diff for: clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c

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Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
2324
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons

Diff for: llvm/lib/Target/AArch64/AArch64Processors.td

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Original file line numberDiff line numberDiff line change
@@ -1015,7 +1015,7 @@ def ProcessorFeatures {
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FeatureCCIDX,
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FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd,
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FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
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FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
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FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
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list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
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FeatureFullFP16, FeatureLS64, FeatureMTE,
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FeaturePerfMon, FeatureRandGen, FeatureSPE,

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