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topperctopperc
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[TableGen][RISCV] Support sub-operands in CompressInstEmitter.cpp. (#133039)
I'm looking into using sub-operands for memory operands. This would use MIOperandInfo to create a single operand that contains a register and immediate as sub-operands. We can treat this as a single operand for parsing and matching in the assembler. I believe this will provide some simplifications like removing the InstAliases we need to support "(rs1)" without an immediate. Doing this requires making CompressInstEmitter aware of sub-operands. I've chosen to use a flat list of operands in the CompressPats so each sub-operand is represented individually.
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‎llvm/test/TableGen/CompressInstEmitter/suboperands.td

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// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../../include %s 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def ArchAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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let AssemblyWriters = [ArchAsmWriter];
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}
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def Reg0 : Register<"reg0"> {
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let HWEncoding{4-0} = 0;
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}
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def Reg1 : Register<"reg1"> {
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let HWEncoding{4-0} = 1;
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}
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def Regs : RegisterClass<"Arch", [i32], 32, (add Reg0, Reg1)>;
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def RegsC : RegisterClass<"Arch", [i32], 32, (sub Regs, Reg0)>;
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def simm6 : Operand<i32>, ImmLeaf<i32, [{return isInt<6>(Imm);}]> {
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isInt<6>(Imm);
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}];
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}
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def simm12 : Operand<i32>, ImmLeaf<i32, [{return isInt<12>(Imm);}]> {
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isInt<12>(Imm);
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}];
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}
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def MemOpnd : Operand<iPTR> {
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let MIOperandInfo = (ops Regs, simm12);
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}
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def MemOpndC : Operand<iPTR> {
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let MIOperandInfo = (ops RegsC, simm6);
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}
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def BigInst : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs Regs:$dst);
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let InOperandList = (ins MemOpnd:$addr);
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let Size = 4;
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let AsmString = "big $dst, $addr";
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}
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def SmallInst : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs RegsC:$dst);
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let InOperandList = (ins MemOpndC:$addr);
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let Size = 2;
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let AsmString = "small $dst, $addr";
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}
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def : CompressPat<(BigInst RegsC:$dst, RegsC:$src, simm6:$imm),
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(SmallInst RegsC:$dst, RegsC:$src, simm6:$imm)>;
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def BigInst2 : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs Regs:$dst);
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let InOperandList = (ins MemOpnd:$addr);
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let Size = 4;
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let AsmString = "big $dst, $addr";
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}
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def SmallInst2 : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs RegsC:$dst);
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let InOperandList = (ins RegsC:$src, simm6:$imm);
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let Size = 2;
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let AsmString = "small $dst, $src, $imm";
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}
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def : CompressPat<(BigInst2 RegsC:$dst, RegsC:$src, simm6:$imm),
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(SmallInst2 RegsC:$dst, RegsC:$src, simm6:$imm)>;
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def BigInst3 : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs Regs:$dst);
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let InOperandList = (ins Regs:$src, simm12:$imm);
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let Size = 4;
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let AsmString = "big $dst, $src, $imm";
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}
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def SmallInst3 : Instruction {
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let Namespace = "MyNS";
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let OutOperandList = (outs RegsC:$dst);
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let InOperandList = (ins MemOpndC:$addr);
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let Size = 2;
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let AsmString = "small $dst, $addr";
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}
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def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
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(SmallInst3 RegsC:$dst, RegsC:$src, simm6:$imm)>;
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// CHECK-LABEL: ArchValidateMCOperandForCompress
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// CHECK: // simm6
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// CHECK: return isInt<6>(Imm);
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// CHECK-LABEL: compressInst
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// CHECK: case Arch::BigInst
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // small $dst, $addr
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// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::BigInst2
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // small $dst, $src, $imm
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// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst2);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: // Operand: imm
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::BigInst3
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // small $dst, $addr
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// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst3);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-LABEL: ArchValidateMCOperandForUncompress
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// CHECK: // simm12
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// CHECK: return isInt<12>(Imm);
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// CHECK-LABEL: uncompressInst
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// CHECK: case Arch::SmallInst:
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // big $dst, $addr
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// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::SmallInst2:
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // big $dst, $addr
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// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst2);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::SmallInst3:
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: ArchValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
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// CHECK-NEXT: // big $dst, $src, $imm
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// CHECK-NEXT: OutInst.setOpcode(Arch::BigInst3);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: // Operand: imm
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(2));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-LABEL: ArchValidateMachineOperand
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// CHECK: // simm6
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// CHECK: return isInt<6>(Imm);
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// CHECK-LABEL: isCompressibleInst
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// CHECK: case Arch::BigInst: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: MI.getOperand(2).isImm() &&
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// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) {
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// CHECK-NEXT: // small $dst, $addr
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::BigInst2: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: MI.getOperand(2).isImm() &&
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// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) {
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// CHECK-NEXT: // small $dst, $src, $imm
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: // Operand: imm
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK: case Arch::BigInst3: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
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// CHECK-NEXT: MI.getOperand(2).isImm() &&
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// CHECK-NEXT: ArchValidateMachineOperand(MI.getOperand(2), &STI, 1)) {
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// CHECK-NEXT: // small $dst, $addr
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: addr
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if

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