[CodeGen][ARM] Missed optimizated load store pair instruction combine

[hstk30-hw]

https://godbolt.org/z/db17KEWK1

typedef struct tagContext {
    unsigned long long int a;
    unsigned long long int b;
    unsigned long long int c;
} Context ;



void test(Context *context) {
    context->a = 0;
    context->b = 0;
    context->c = 0;
}

GCC output:

test:
        movs    r2, #0
        movs    r3, #0
        strd    r2, [r0]
        strd    r2, [r0, #8]
        strd    r2, [r0, #16]
        bx      lr

llvm output:

test:
        mov     r1, #0
        str     r1, [r0]
        str     r1, [r0, #4]
        str     r1, [r0, #8]
        str     r1, [r0, #12]
        str     r1, [r0, #16]
        str     r1, [r0, #20]
        bx      lr

ARMLoadStoreOptimizer Pass have Pre/post register allocation

[llvmbot]

@llvm/issue-subscribers-backend-arm

Author: None (hstk30-hw)

https://godbolt.org/z/db17KEWK1

typedef struct tagContext {
    unsigned long long int a;
    unsigned long long int b;
    unsigned long long int c;
} Context ;



void test(Context *context) {
    context->a = 0;
    context->b = 0;
    context->c = 0;
}

GCC output:

test:
        movs    r2, #<!-- -->0
        movs    r3, #<!-- -->0
        strd    r2, [r0]
        strd    r2, [r0, #<!-- -->8]
        strd    r2, [r0, #<!-- -->16]
        bx      lr

llvm output:

test:
        mov     r1, #<!-- -->0
        str     r1, [r0]
        str     r1, [r0, #<!-- -->4]
        str     r1, [r0, #<!-- -->8]
        str     r1, [r0, #<!-- -->12]
        str     r1, [r0, #<!-- -->16]
        str     r1, [r0, #<!-- -->20]
        bx      lr

ARMLoadStoreOptimizer Pass have Pre/post register allocation

[davemgreen]

GCC might be defaulting to -mthumb, which would allow it to use STRD on llvm: https://godbolt.org/z/cfKzYnPfh. Otherwise the A32 instruction requires consecutive registers so it more difficult to use.

[hstk30-hw]

GCC after 9.3.0 default to -mthumb possibly. In 8.5.0 can still use STRD.
https://godbolt.org/z/4aE1d3dhj

[hstk30-hw]

Hi, why llvm generate

strd    r1, r1, [r0]

I see the STRD need consecutive registers. Thumb not have this limit? I can't find thumb's document.

https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Instruction-Details/Alphabetical-list-of-instructions/STRD--register-

[davemgreen]

The immediate version has T1 and A1 versions: https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Instruction-Details/Alphabetical-list-of-instructions/STRD--immediate-

Yeah - the arm instruction needs consecutive instructions, the thumb variant does not. The register allocator does not know that it is beneficial to duplicate the mov to make use of the strd instruction.

Have you considered using -mthumb? Or is there a reason you cannot use it? The extra code-density itself can be good benefit. We should maybe be considering changing the default to -mthumb to match GCC.

[hstk30-hw]

Emm, I can use -mthumb, but not sure how the performance.
In fact, I'm doing some performance improve work in A32, then find this difference between GCC : )

[pinskia]

GCC after 9.3.0 default to -mthumb possibly. In 8.5.0 can still use STRD. https://godbolt.org/z/4aE1d3dhj

Note it is not GCC defaults that change but rather godbolt's configuration of gcc that changed between the versions.

[hstk30-hw]

Thanks for the correction.

Note it is not GCC defaults that change but rather godbolt's configuration of gcc that changed between the versions.