[AMDGPU] add tests for loop definition of bitconvert #133052
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@llvm/pr-subscribers-backend-amdgpu Author: None (Shoreshen) ChangesAll tests passed due to:
define <2 x double> @v_bitcast_v4f32_to_v2f64(<4 x float> inreg %a, i32 %b) { cmp.true: cmp.false: end: |
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Please add Also what are these lit tests for ? why do we need to test all widths? |
Shoreshen
changed the title
Hi @Pierre-vh , this is adding test PR for #132899, which using loop in tablegen to generate bitconvert patterns, instead of doing it one by one.... Thanks~ |
Every operation with every type should be tested. For this case, we already should have test coverage so I'm not sure I understand what is new here. We should perhaps split / replace the existing test with a more consistent pattern, but this patch is purely additive? |
arsenm
reviewed
Mar 27, 2025
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX9 %s | ||
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-codegenprepare-break-large-phis-threshold=4096 < %s | FileCheck -check-prefixes=GFX11 %s | ||
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| define <5 x float> @v_bitcast_v5i32_to_v5f32(<5 x i32> %a, i32 %b) { |
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Doesn't have scalar version
Hi @arsenm , I removed the old tests and split them into different files named by bit width. |
shiltian
approved these changes
Apr 7, 2025
arsenm
reviewed
Apr 8, 2025
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s | ||
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s | ||
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| define amdgpu_kernel void @bitcast_i8ptr_v16i8ptr(ptr addrspace(1) %out, ptr addrspace(1) %in) { |
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Why "ptr" in the name? There is no pointer cast here. This is also not testing the reverse direction, or all of the interesting type sizes. I think we should be generating all of the cases
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Hi @arsenm , this case is a copy from the old file llvm-project/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll: L56~L116:
define amdgpu_kernel void @i8ptr_v16i8ptr(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GCN-LABEL: i8ptr_v16i8ptr:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v3, s7
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; VI-LABEL: i8ptr_v16i8ptr:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s6
; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: i8ptr_v16i8ptr:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: i8ptr_v16i8ptr:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%0 = load <16 x i8>, ptr addrspace(1) %in
store <16 x i8> %0, ptr addrspace(1) %out
ret void
}
I'm kind of not sure how I should handle this because there is no bitcast.....
| @@ -0,0 +1,68 @@ | |||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 | |||
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| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s | |||
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Avoid using the default target. -mcpu=tahiti? Also extra spaces before <
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Currently not convinced we aren't losing test coverage. The content of some of the new bitwidth suffixed files don't have enough functions to justify splitting up. I'd prefer generated, wholly consistent tests with the suffixes if we're splitting this up
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/16963 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/187/builds/5281 Here is the relevant piece of the build log for the reference |
This was referenced Apr 8, 2025
Shoreshen
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Apr 8, 2025
function `bitcast_v64i16_to_v128i8` in newly added test file `llvm-project/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll` from PR:#133052 failed in expansive check. (passes normal lit check) remove it for now
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Apr 8, 2025
function `bitcast_v64i16_to_v128i8` in newly added test file `llvm-project/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll` from PR:llvm/llvm-project#133052 failed in expansive check. (passes normal lit check) remove it for now
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This PR add test cases for all types of bit conversation, it prepares for PR: #132899
All tests passed due to:
Select_COPYto select bitcast