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Merged
merged 2 commits into from
Mar 27, 2025
Merged

[RISCV] Use a precise size for MMO on scalable spill and fill #133171

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[RISCV] Use a precise size for MMO on scalable spill and fill
preames Mar 26, 2025
78031d4
Merge branch 'main' into pr-riscv-typesize-spill-fill
preames Mar 26, 2025
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11 changes: 8 additions & 3 deletions llvm/lib/CodeGen/MachineInstr.cpp
View file
Original file line number Diff line number Diff line change
@@ -2525,18 +2525,23 @@ using MMOList = SmallVector<const MachineMemOperand *, 2>;

static LocationSize getSpillSlotSize(const MMOList &Accesses,
const MachineFrameInfo &MFI) {
uint64_t Size = 0;
std::optional<TypeSize> Size;
for (const auto *A : Accesses) {
if (MFI.isSpillSlotObjectIndex(
cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
->getFrameIndex())) {
LocationSize S = A->getSize();
if (!S.hasValue())
return LocationSize::beforeOrAfterPointer();
Size += S.getValue();
if (!Size)
Size = S.getValue();
else
Size = *Size + S.getValue();
}
}
return Size;
if (!Size)
return LocationSize::precise(0);
return LocationSize::precise(*Size);
}

std::optional<LocationSize>
8 changes: 6 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
@@ -705,9 +705,11 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
llvm_unreachable("Can't store this register to stack slot");

if (IsScalableVector) {
LocationSize LocSize =
LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
LocationSize::beforeOrAfterPointer(), MFI.getObjectAlign(FI));
LocSize, MFI.getObjectAlign(FI));

MFI.setStackID(FI, TargetStackID::ScalableVector);
BuildMI(MBB, I, DebugLoc(), get(Opcode))
@@ -797,9 +799,11 @@ void RISCVInstrInfo::loadRegFromStackSlot(
llvm_unreachable("Can't load this register from stack slot");

if (IsScalableVector) {
LocationSize LocSize =
LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
LocationSize::beforeOrAfterPointer(), MFI.getObjectAlign(FI));
LocSize, MFI.getObjectAlign(FI));

MFI.setStackID(FI, TargetStackID::ScalableVector);
BuildMI(MBB, I, DL, get(Opcode), DstReg)
11 changes: 9 additions & 2 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
View file
Original file line number Diff line number Diff line change
@@ -406,6 +406,10 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
Register Base = II->getOperand(1).getReg();
bool IsBaseKill = II->getOperand(1).isKill();
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);

auto *OldMMO = *(II->memoperands_begin());
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
LocationSize::beforeOrAfterPointer());
for (unsigned I = 0; I < NF; ++I) {
// Adding implicit-use of super register to describe we are using part of
// super register, that prevents machine verifier complaining when part of
@@ -414,7 +418,7 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
BuildMI(MBB, II, DL, TII->get(Opcode))
.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
.addReg(Base, getKillRegState(I == NF - 1))
.addMemOperand(*(II->memoperands_begin()))
.addMemOperand(NewMMO)
.addReg(SrcReg, RegState::Implicit);
if (I != NF - 1)
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
@@ -483,11 +487,14 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
Register Base = II->getOperand(1).getReg();
bool IsBaseKill = II->getOperand(1).isKill();
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
auto *OldMMO = *(II->memoperands_begin());
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
LocationSize::beforeOrAfterPointer());
for (unsigned I = 0; I < NF; ++I) {
BuildMI(MBB, II, DL, TII->get(Opcode),
TRI->getSubReg(DestReg, SubRegIdx + I))
.addReg(Base, getKillRegState(I == NF - 1))
.addMemOperand(*(II->memoperands_begin()));
.addMemOperand(NewMMO);
if (I != NF - 1)
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
.addReg(Base, getKillRegState(I != 0 || IsBaseKill))
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
View file
Original file line number Diff line number Diff line change
@@ -32,7 +32,7 @@ define void @_Z3foov() {
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_46)
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_46)
; CHECK-NEXT: vle16.v v10, (a0)
@@ -72,7 +72,7 @@ define void @_Z3foov() {
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v14, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, mu
; CHECK-NEXT: vsext.vf2 v8, v14, v0.t
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_44)
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
View file
Original file line number Diff line number Diff line change
@@ -64,7 +64,7 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb
; RV32-NEXT: addi a0, sp, 32
; RV32-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: srli a0, a0, 3
; RV32-NEXT: li a2, 8
@@ -79,7 +79,7 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
; RV32-NEXT: vid.v v8
; RV32-NEXT: li a2, -1
; RV32-NEXT: addi a3, sp, 32
; RV32-NEXT: vl2r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vl2r.v v24, (a3) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmsne.vi v0, v24, 0
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/pr69586.ll
View file
Original file line number Diff line number Diff line change
@@ -102,7 +102,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: sf.vc.vv 3, 0, v8, v10
; NOREMAT-NEXT: vle32.v v8, (a4)
; NOREMAT-NEXT: addi a0, sp, 640
; NOREMAT-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; NOREMAT-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
; NOREMAT-NEXT: add a4, a7, t4
; NOREMAT-NEXT: vle32.v v10, (a4)
; NOREMAT-NEXT: sf.vc.vv 3, 0, v2, v0
@@ -377,7 +377,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; NOREMAT-NEXT: vle32.v v14, (a2)
; NOREMAT-NEXT: vle32.v v30, (a2)
; NOREMAT-NEXT: addi a0, sp, 640
; NOREMAT-NEXT: vl2r.v v12, (a0) # Unknown-size Folded Reload
; NOREMAT-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; NOREMAT-NEXT: sf.vc.vv 3, 0, v12, v22
; NOREMAT-NEXT: addiw a2, s0, -512
; NOREMAT-NEXT: sd a2, 336(sp) # 8-byte Folded Spill
@@ -998,7 +998,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a2, a2, 4
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v6, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, t2
; REMAT-NEXT: vle32.v v4, (a0)
; REMAT-NEXT: vle32.v v2, (a2)
@@ -1008,7 +1008,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a2, a2, a5
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v6, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v6, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, t3
; REMAT-NEXT: sf.vc.vv 3, 0, v4, v8
; REMAT-NEXT: vle32.v v4, (a2)
@@ -1027,7 +1027,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a2, a2, a5
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, t6
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v20, v22
@@ -1046,7 +1046,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a5, a5, 4
; REMAT-NEXT: add a5, sp, a5
; REMAT-NEXT: addi a5, a5, 432
; REMAT-NEXT: vl2r.v v12, (a5) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v12, (a5) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v2
; REMAT-NEXT: vle32.v v2, (a2)
; REMAT-NEXT: add a2, a0, s3
@@ -1056,7 +1056,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a5, a5, a6
; REMAT-NEXT: add a5, sp, a5
; REMAT-NEXT: addi a5, a5, 432
; REMAT-NEXT: vl2r.v v16, (a5) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v16, (a5) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
; REMAT-NEXT: vle32.v v30, (a2)
; REMAT-NEXT: add a2, a0, s4
@@ -1074,7 +1074,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a5, a5, a6
; REMAT-NEXT: add a5, sp, a5
; REMAT-NEXT: addi a5, a5, 432
; REMAT-NEXT: vl2r.v v0, (a5) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v0, (a5) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v0, v18
; REMAT-NEXT: vle32.v v0, (a2)
; REMAT-NEXT: add a2, a0, s7
@@ -1097,7 +1097,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a2, a2, 3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v12, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v12, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, s11
; REMAT-NEXT: vle32.v v12, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v30, v16
@@ -1110,7 +1110,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a2, a2, 1
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v10, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, a4
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v4, v14
@@ -1119,7 +1119,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a2, a2, 2
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v14, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v14, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: add a2, a0, a3
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: sf.vc.vv 3, 0, v0, v18
@@ -1128,21 +1128,21 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a2, a2, 4
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v18, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v18, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: li a5, 7
; REMAT-NEXT: slli a5, a5, 11
; REMAT-NEXT: add a2, a0, a5
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: addi a3, sp, 432
; REMAT-NEXT: vs2r.v v18, (a3) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v18, (a3) # vscale x 16-byte Folded Spill
; REMAT-NEXT: sf.vc.vv 3, 0, v22, v20
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: csrr a2, vlenb
; REMAT-NEXT: li a3, 14
; REMAT-NEXT: mul a2, a2, a3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v18, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v18, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: li a2, 29
; REMAT-NEXT: slli a2, a2, 9
; REMAT-NEXT: add a2, a0, a2
@@ -1154,7 +1154,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a2, a2, a3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v20, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v20, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: li a2, 15
; REMAT-NEXT: slli a2, a2, 10
; REMAT-NEXT: add a2, a0, a2
@@ -1166,7 +1166,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a2, a2, a3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: li a2, 31
; REMAT-NEXT: slli a2, a2, 9
; REMAT-NEXT: add a2, a0, a2
@@ -1175,14 +1175,14 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a3, a3, 3
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v12
; REMAT-NEXT: vle32.v v8, (a2)
; REMAT-NEXT: csrr a2, vlenb
; REMAT-NEXT: slli a2, a2, 3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: lui a2, 4
; REMAT-NEXT: add a2, a0, a2
; REMAT-NEXT: vle32.v v4, (a2)
@@ -1193,7 +1193,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a2, a2, a3
; REMAT-NEXT: add a2, sp, a2
; REMAT-NEXT: addi a2, a2, 432
; REMAT-NEXT: vs2r.v v8, (a2) # Unknown-size Folded Spill
; REMAT-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; REMAT-NEXT: lui a2, 4
; REMAT-NEXT: addiw a2, a2, 512
; REMAT-NEXT: add a2, a0, a2
@@ -1202,7 +1202,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a3, a3, 1
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v10
; REMAT-NEXT: vle32.v v20, (a2)
; REMAT-NEXT: li a2, 17
@@ -1213,7 +1213,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a3, a3, 2
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v14
; REMAT-NEXT: vle32.v v22, (a2)
; REMAT-NEXT: lui a2, 4
@@ -1224,9 +1224,9 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a3, a3, 4
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v8, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: addi a3, sp, 432
; REMAT-NEXT: vl2r.v v10, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v10, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v8, v10
; REMAT-NEXT: vle32.v v8, (a2)
; REMAT-NEXT: li a2, 9
@@ -1238,7 +1238,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a3, a3, a4
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v10, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v10, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v10, v18
; REMAT-NEXT: vle32.v v10, (a2)
; REMAT-NEXT: lui a2, 5
@@ -1250,7 +1250,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a3, a3, a4
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v12, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v12, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v12, v30
; REMAT-NEXT: vle32.v v12, (a2)
; REMAT-NEXT: li a2, 19
@@ -1262,7 +1262,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a3, a3, a4
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v14, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v14, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v14, v6
; REMAT-NEXT: vle32.v v14, (a2)
; REMAT-NEXT: lui a2, 5
@@ -1273,7 +1273,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: slli a3, a3, 3
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v16, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v16, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v16, v4
; REMAT-NEXT: vle32.v v16, (a2)
; REMAT-NEXT: lui a2, 5
@@ -1284,7 +1284,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
; REMAT-NEXT: mul a3, a3, a4
; REMAT-NEXT: add a3, sp, a3
; REMAT-NEXT: addi a3, a3, 432
; REMAT-NEXT: vl2r.v v18, (a3) # Unknown-size Folded Reload
; REMAT-NEXT: vl2r.v v18, (a3) # vscale x 16-byte Folded Reload
; REMAT-NEXT: sf.vc.vv 3, 0, v18, v2
; REMAT-NEXT: vle32.v v18, (a2)
; REMAT-NEXT: lui a2, 5
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