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[RISCV] Use TypeSize instead of uint64_t in getMachineMemOperand interface #133274

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preames
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@preames preames commented Mar 27, 2025

The primary reason is that if you pass a TypeSize without explicitly converting to LocationSize, you otherwise implicit convert to uint64_t to call the respective LocationSize constructor. This means that any scalable value becomes a runtime assertion failure.

By replacing uint64_t with TypeSize in this API, we avoid the implicit conversion for TypeSize. uint64_t callers implicit convert to LocationSize (via the raw constructor) which should have unchanged behavior.

…rface

The primary reason is that if you pass a TypeSize without explicitly
converting to LocationSize, you otherwise implicit convert to uint64_t
to call the respective LocationSize constructor.  This means that any
scalable value becomes a runtime assertion failure.

By replacing uint64_t with TypeSize in this API, we avoid the implicit
convertion for TypeSize.  uint64_t callers implicit convert to
LocationSize (via the raw constructor) which should have unchanged
behavior.
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llvmbot commented Mar 27, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Philip Reames (preames)

Changes

The primary reason is that if you pass a TypeSize without explicitly converting to LocationSize, you otherwise implicit convert to uint64_t to call the respective LocationSize constructor. This means that any scalable value becomes a runtime assertion failure.

By replacing uint64_t with TypeSize in this API, we avoid the implicit conversion for TypeSize. uint64_t callers implicit convert to LocationSize (via the raw constructor) which should have unchanged behavior.


Full diff: https://github.com/llvm/llvm-project/pull/133274.diff

2 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+3-3)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+2-6)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 9a4d990bd0afa..429dd54de33c2 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1073,7 +1073,7 @@ class LLVM_ABI MachineFunction {
       AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
       AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
   MachineMemOperand *getMachineMemOperand(
-      MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, uint64_t Size,
+      MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize Size,
       Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
       const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
       AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
@@ -1099,7 +1099,7 @@ class LLVM_ABI MachineFunction {
             : LLT::scalar(8 * Size.getValue().getKnownMinValue()));
   }
   MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
-                                          int64_t Offset, uint64_t Size) {
+                                          int64_t Offset, TypeSize Size) {
     return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
   }
 
@@ -1115,7 +1115,7 @@ class LLVM_ABI MachineFunction {
                                           LLT Ty);
   MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
                                           const MachinePointerInfo &PtrInfo,
-                                          uint64_t Size) {
+                                          TypeSize Size) {
     return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
   }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 84e44571a451a..02f56b7ce5326 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -705,11 +705,9 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     llvm_unreachable("Can't store this register to stack slot");
 
   if (IsScalableVector) {
-    LocationSize LocSize =
-        LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
-        LocSize, MFI.getObjectAlign(FI));
+        TypeSize::getScalable(MFI.getObjectSize(FI)), MFI.getObjectAlign(FI));
 
     MFI.setStackID(FI, TargetStackID::ScalableVector);
     BuildMI(MBB, I, DebugLoc(), get(Opcode))
@@ -799,11 +797,9 @@ void RISCVInstrInfo::loadRegFromStackSlot(
     llvm_unreachable("Can't load this register from stack slot");
 
   if (IsScalableVector) {
-    LocationSize LocSize =
-        LocationSize::precise(TypeSize::getScalable(MFI.getObjectSize(FI)));
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
-        LocSize, MFI.getObjectAlign(FI));
+        TypeSize::getScalable(MFI.getObjectSize(FI)), MFI.getObjectAlign(FI));
 
     MFI.setStackID(FI, TargetStackID::ScalableVector);
     BuildMI(MBB, I, DL, get(Opcode), DstReg)

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LGTM

@preames preames merged commit d584cea into llvm:main Mar 27, 2025
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@preames preames deleted the pr-riscv-getMachineMemoryOperand-typesize branch March 27, 2025 18:04
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3 participants