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[RISCV] Add additional RISC-V 2-stage cross-compile and test under qemu-system configs #479

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Merged
merged 1 commit into from
Jun 20, 2025
Merged

[RISCV] Add additional RISC-V 2-stage cross-compile and test under qemu-system configs #479

merged 1 commit into from
Jun 20, 2025

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asb
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@asb asb commented Jun 19, 2025

This adds:

  • rva23 with zvl512b
  • rva23 with zvl1024b
  • -mcpu=spacemit-x60 with -mrvv-vector-bits=zvl (this config also gives zvl256b coverage)

@asb
[RISCV] Add additional RISC-V 2-stage cross-compile and test under qe…
89230a5 
…mu-system configs

This adds:
* rva23 with zvl512b
* rva23 with zvl1024b
* -mcpu=spacemit-x60 with -mrvv-vector-bits=zvl (this config also gives
  zvl256b coverage)
lukel97
lukel97 approved these changes Jun 19, 2025
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LGTM

@asb asb merged commit 49f238d into llvm:main Jun 20, 2025
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