We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Modular hardware build system
Python 1.1k 109
SiliconCompiler Design Gallery
Verilog 51 6
Hardware abstraction library
Verilog 34 5
Library of open source Process Design Kits (PDKs)
SourcePawn 50 7
Demo SoC for SiliconCompiler.
SystemVerilog 59 9
A configurable RTL to bitstream FPGA toolchain
Python 38 5
There was an error while loading. Please reload this page.
Library of FPGA architectures
Yosys Open SYnthesis Suite
Loading…