G0: update CMSIS Cortex-Mx Device Peripheral Access Layer System Source File

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>

Author: fpistm

system/STM32G0xx/system_stm32g0xx.c

@@ -56,10 +56,10 @@
   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -214,30 +214,30 @@ void SystemCoreClockUpdate(void)
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (RCC->CFGR & RCC_CFGR_SWS)
   {
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+    case RCC_CFGR_SWS_0:                /* HSE used as system clock */
       SystemCoreClock = HSE_VALUE;
       break;
 
-    case RCC_CFGR_SWS_LSI:  /* LSI used as system clock */
+    case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0):  /* LSI used as system clock */
       SystemCoreClock = LSI_VALUE;
       break;
 
-    case RCC_CFGR_SWS_LSE:  /* LSE used as system clock */
+    case RCC_CFGR_SWS_2:                /* LSE used as system clock */
       SystemCoreClock = LSE_VALUE;
       break;
 
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+    case RCC_CFGR_SWS_1:  /* PLL used as system clock */
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
          SYSCLK = PLL_VCO / PLLR
          */
       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
 
-      if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      if(pllsource == 0x03UL)           /* HSE used as PLL clock source */
       {
         pllvco = (HSE_VALUE / pllm);
       }
-      else /* HSI used as PLL clock source */
+      else                              /* HSI used as PLL clock source */
       {
           pllvco = (HSI_VALUE / pllm);
       }
@@ -247,8 +247,8 @@ void SystemCoreClockUpdate(void)
       SystemCoreClock = pllvco/pllr;
       break;
 
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-    default:                /* HSI used as system clock */
+    case 0x00000000U:                   /* HSI used as system clock */
+    default:                            /* HSI used as system clock */
       hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
       SystemCoreClock = (HSI_VALUE/hsidiv);
       break;