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system(F0): update STM32F0xx CMSIS Drivers to v2.3.7
Included in STM32CubeF0 FW v1.11.4 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 57637a3 commit cce7f32

40 files changed

+23624
-23731
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h

+15-17
Original file line numberDiff line numberDiff line change
@@ -9,22 +9,20 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
27-
2826
/** @addtogroup CMSIS
2927
* @{
3028
*/
@@ -70,7 +68,7 @@ typedef enum
7068
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
7169
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7270
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
73-
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
71+
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
7472
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
7573
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
7674

@@ -549,7 +547,7 @@ typedef struct
549547
/******************************************************************************/
550548

551549
/*
552-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
550+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
553551
*/
554552
/* Note: No specific macro feature on this device */
555553

@@ -637,7 +635,7 @@ typedef struct
637635

638636
#define ADC_CFGR1_ALIGN_Pos (5U)
639637
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
640-
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
638+
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
641639

642640
#define ADC_CFGR1_EXTSEL_Pos (6U)
643641
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -2731,7 +2729,7 @@ typedef struct
27312729
/* */
27322730
/*****************************************************************************/
27332731
/*
2734-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
2732+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
27352733
*/
27362734

27372735
/******************** Bit definition for RCC_CR register *******************/
@@ -3290,7 +3288,7 @@ typedef struct
32903288
/* */
32913289
/*****************************************************************************/
32923290
/*
3293-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3291+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
32943292
*/
32953293
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
32963294
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -3750,7 +3748,7 @@ typedef struct
37503748
/*****************************************************************************/
37513749

37523750
/*
3753-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3751+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
37543752
*/
37553753
/* Note: No specific macro feature on this device */
37563754

@@ -5337,17 +5335,18 @@ typedef struct
53375335
#define ADC1_COMP_IRQn ADC1_IRQn
53385336
#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
53395337
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
5340-
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
53415338
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5339+
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
53425340
#define RCC_CRS_IRQn RCC_IRQn
53435341

5342+
#define SVC_IRQn SVCall_IRQn
53445343

53455344
/* Aliases for __IRQHandler */
53465345
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
53475346
#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
53485347
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
5349-
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
53505348
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
5349+
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
53515350
#define RCC_CRS_IRQHandler RCC_IRQHandler
53525351

53535352

@@ -5365,4 +5364,3 @@ typedef struct
53655364
* @}
53665365
*/
53675366

5368-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h

+15-17
Original file line numberDiff line numberDiff line change
@@ -9,22 +9,20 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
27-
2826
/** @addtogroup CMSIS
2927
* @{
3028
*/
@@ -70,7 +68,7 @@ typedef enum
7068
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
7169
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7270
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
73-
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
71+
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
7472
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
7573
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
7674

@@ -565,7 +563,7 @@ typedef struct
565563
/******************************************************************************/
566564

567565
/*
568-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
566+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
569567
*/
570568
/* Note: No specific macro feature on this device */
571569

@@ -653,7 +651,7 @@ typedef struct
653651

654652
#define ADC_CFGR1_ALIGN_Pos (5U)
655653
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
656-
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
654+
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
657655

658656
#define ADC_CFGR1_EXTSEL_Pos (6U)
659657
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -2761,7 +2759,7 @@ typedef struct
27612759
/* */
27622760
/*****************************************************************************/
27632761
/*
2764-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
2762+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
27652763
*/
27662764

27672765
/******************** Bit definition for RCC_CR register *******************/
@@ -3334,7 +3332,7 @@ typedef struct
33343332
/* */
33353333
/*****************************************************************************/
33363334
/*
3337-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3335+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
33383336
*/
33393337
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
33403338
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -3794,7 +3792,7 @@ typedef struct
37943792
/*****************************************************************************/
37953793

37963794
/*
3797-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3795+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
37983796
*/
37993797
/* Note: No specific macro feature on this device */
38003798

@@ -5402,18 +5400,19 @@ typedef struct
54025400
#define ADC1_COMP_IRQn ADC1_IRQn
54035401
#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
54045402
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
5405-
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
54065403
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
5404+
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
54075405
#define RCC_CRS_IRQn RCC_IRQn
54085406
#define TIM6_DAC_IRQn TIM6_IRQn
54095407

5408+
#define SVC_IRQn SVCall_IRQn
54105409

54115410
/* Aliases for __IRQHandler */
54125411
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
54135412
#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
54145413
#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
5415-
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
54165414
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
5415+
#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
54175416
#define RCC_CRS_IRQHandler RCC_IRQHandler
54185417
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
54195418

@@ -5432,4 +5431,3 @@ typedef struct
54325431
* @}
54335432
*/
54345433

5435-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030xc.h

+16-18
Original file line numberDiff line numberDiff line change
@@ -9,22 +9,20 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2016 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
27-
2826
/** @addtogroup CMSIS
2927
* @{
3028
*/
@@ -70,7 +68,7 @@ typedef enum
7068
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
7169
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
7270
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
73-
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
71+
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
7472
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
7573
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
7674

@@ -581,7 +579,7 @@ typedef struct
581579
/******************************************************************************/
582580

583581
/*
584-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
582+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
585583
*/
586584
/* Note: No specific macro feature on this device */
587585

@@ -669,7 +667,7 @@ typedef struct
669667

670668
#define ADC_CFGR1_ALIGN_Pos (5U)
671669
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
672-
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
670+
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
673671

674672
#define ADC_CFGR1_EXTSEL_Pos (6U)
675673
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -3024,7 +3022,7 @@ typedef struct
30243022
/* */
30253023
/*****************************************************************************/
30263024
/*
3027-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3025+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
30283026
*/
30293027
#define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */
30303028

@@ -3140,8 +3138,8 @@ typedef struct
31403138
#define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
31413139
#define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
31423140

3143-
#define RCC_CFGR_PLLSRC_Pos (16U)
3144-
#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
3141+
#define RCC_CFGR_PLLSRC_Pos (15U)
3142+
#define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
31453143
#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
31463144
#define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
31473145
#define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */
@@ -3636,7 +3634,7 @@ typedef struct
36363634
/* */
36373635
/*****************************************************************************/
36383636
/*
3639-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3637+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
36403638
*/
36413639
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
36423640
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -4120,7 +4118,7 @@ typedef struct
41204118
/*****************************************************************************/
41214119

41224120
/*
4123-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
4121+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
41244122
*/
41254123
/* Note: No specific macro feature on this device */
41264124

@@ -5092,7 +5090,7 @@ typedef struct
50925090
/******************************************************************************/
50935091

50945092
/*
5095-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
5093+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
50965094
*/
50975095

50985096
/* Support of 7 bits data length feature */
@@ -5784,6 +5782,7 @@ typedef struct
57845782
#define USART3_8_IRQn USART3_6_IRQn
57855783
#define USART3_4_IRQn USART3_6_IRQn
57865784

5785+
#define SVC_IRQn SVCall_IRQn
57875786

57885787
/* Aliases for __IRQHandler */
57895788
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
@@ -5811,4 +5810,3 @@ typedef struct
58115810
* @}
58125811
*/
58135812

5814-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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