Skip to content
#

rtl-verification

Star

Here are 2 public repositories matching this topic...

Language: All
Filter by language
All 2 SystemVerilog 1 Verilog 1

ramiomer94 / VLSI-design-projects

Star 0

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools
  • Updated Jul 12, 2025
  • Verilog

Improve this page

Add a description, image, and links to the rtl-verification topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the rtl-verification topic, visit your repo's landing page and select "manage topics."

Learn more