MimasA7-SLI

This repository serves a structured light illumination (SLI) system orchestrated by an FPGA controller. The system is based on the Numato Mimas A7 Rev3 board, which is powered by an Artix-7 FPGA. The board includes two HDMI shields: one for input and one for output.

In this project, the FPGA:

• Takes HDMI video input from a host PC and outputs HDMI video to a DLP projector.
• Can replace the HDMI input frames to play SLI patterns.
• If the HDMI input is absent (offline mode), the FPGA generates the SLI pattern using the local clock source.
• Synchronizes the projection and capture of each frame by interacting with a PC and a camera module through the GPIO header using a handshake protocol.
• Utilizes a customized PCB to bridge the GPIO header with the PC and camera via a DB9 port.

The camera module captures SLI patterns reflected by the scanned object and provides them to the host PC for 3-D reconstruction. The system can scan 800x600 resolution at 120FPS. A photo of the protoypr is shown below.

How to configure the bitstream?

1. Download and install the latest version of Tenagra FPGA System Manager from NumatoLab.
2. Download Bitstream\Mimas-SLI.bin to your local machine.
3. Power on the Mimas A7 board and connect it to your PC via USB.
4. Open Tenagra => Program Device => select Flash Memory => click Add More Configurations => select Mimas-SLI.bin=> click Run => wait until the GUI confirms that the configuration is completed successfully.

FPGA Controller Modes

1. Pass-through with Top-Left Pixel Detection

• The FPGA functions as an HDMI pass-through capable of 720p@60Hz. The PC is responsible for playing back the SLI patterns.
• The FPGA reads the top-left pixel (TLP) value of each frame and displays it (in hexadecimal) on a 7-segment display.
• If the current frame has a different TLP value from the previous frame, the FPGA sends a pulse to trigger the camera shutter during the next VSYNC period.
• The host PC waits for confirmation that the camera is ready before playing the next frame.

2. Pass-through with SLI Pattern Generation

• The FPGA takes input from the HDMI source and replaces the visible pixels of each frame with those from a predefined pattern before passing them to the HDMI output.
• The pattern is a 24-frame sequence, split into three 8-frame groups, each with a different spatial frequency. The sequence is followed by a 8-frame flashing sequenc made of pure black/white frames. A LUT defines the pixel values of the start frame.
• For top-down scanning, indexMapping.m maps the combination of a pixel’s row index and frame index to an index in the LUT.
• For side-to-side scanning, indexMappingV.m maps the combination of a pixel’s col index and frame index to an index in the LUT.
• The LUT is pre-generated as LUT.txt and LUT_V.txt for both scanning directions, txt2raw.m convert them into one binary file (LUT.raw) that is stored in the SD card.
• Each pixel’s row index is mapped to the corresponding LUT index using a read-only memory (ROM) module, initialized by a coefficient file (indexMap.coe) generated by the indexMapping.m script.
• Each pixel’s col index is mapped to the corresponding LUT index using a read-only memory (ROM) module, initialized by a coefficient file (indexMapV.coe) generated by the indexMappingV.m script.
• The FPGA increments the frame index and triggers the camera on VSYNC, as long as it detects of a rising-edge of the trigger-ready input.

3. Offline Mode

When the HDMI input is absent, the FPGA enters offline mode. This mode is similar to Mode #2, but the pattern is generated using the local oscillator clock. The pattern is projected at a fixed resolution of 800x600 at 120Hz. However, this board has cross-talk issues, resulting in an active hdmi_rx_clk signal even when no cable is plugged in. So we use DIP Switch #4 to manually choose between offline and online modes.

Tips for setting FPS and resoultion for HDMI Input

The HDMI input should be automtcially conifgured after it reads the EDID from the FPGA. To confirm it in Windows, go to System > Display > Advanced Settings > Sletect Display "Qishi-SLI". The display info should be similar to the screenshot below.

The Active Signal Mode is the actual setting of the HDMI signal, if it is not for 800x600@120Hz, please go to System > Display > Advanced Settings > Adapter Properties > List All Modes to manually set it.

LED, Push Buttons, and DIP Swicthes

1. LED indicators

LED (Index)	Indication
7	VSYNC
6	HSYNC
5	VYSNC Polarity (1 for postive, 0 for negative)
4	On for pass-through mode, off for offline mode
3	0 for SLI pattern, 1 for desktop dispaly (black screen if in offline mode)
2	On if camera trigger is ready
1	On if the current frame is the first frame of the pattern
0	Trigger Output

• LED0 is the one closest to the GPIO header

2. 7-segment display (two digits enabled)

For passthrough mode with TL pixel detection, it shows the TLP value in hexdecimal. For SLI pattern palyback, one digit represent the current spatial frequency index (0-2) and the other digit represents the frame/phase index (0-7) under the current spatial frequency. If it shows "88" after boot up, that means no valid input pixel clock as each segment is set to default value '0' (on).

3. BTNU push button

This button is located right next to the Artix-7 trademark. It can be used to reset the HDMI output port during runtime.

4. DIP Switches Control

SW (Index)	Function
8	On to disable the Red channel
7	On to disable the Green channel
6	On to disable the Blue channel
5	Unused
4	On to enter offline mode, Off for pass-trhough
3	Unused
2	On for vertical stripes, Off for horizontal stripes
1	Unused

GPIO pin assignments

BASLR Cam	FPGA Pins	DB9 Pins	Purpose	I/O (from FPGA's POV)
Line 1	A31_1	5	Trigger the camera	Output
Line 2	A28_1	9	Mode (1 for SD pattern, 0 for pass-through)	Input
Line 3	A29_1	4	First frame of the pattern	Output
Line 4	A32_1	8	Camera is ready for the next trigger	Input
GND	A40_1	1	Ground	-
VCC(3.3V)	A9_1		3.3 V reference for the PCB	-

Directory Structure

├── README.md           # Overview of the repository  
├── MimasA7_SLI.zip    # Archive of the Vivado 2024.1 project  
├── Bitsrteam/          # Final bitstream files  
├── Matlab/             # .m scripts and output files  
├── src_1/              # Source HDLand Matlab code  
└── constr_1/           #  Xlinx Design Constarint  

Example Phase Images Captured by Basler Camera and Gradient Map Generated by PC Host Program

Licensing

Building an HDMI pass-through is a foundational element of this project. For this, I adapted the design by hamsternz (MIT License).