👋 Hi, I'm Praveen Kumar

🎓 VLSI Enthusiast | RTL & Verification Learner | FPGA/ASIC Design Explorer | Open Source Contributor


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🛠️ I’m passionate about digital design, hardware description languages (HDLs), and building real-world projects using SystemVerilog, Verilog, and FPGA boards. My journey into VLSI is driven by curiosity, hands-on experimentation, and a desire to master the tools and techniques that power modern chip design.

🧠 Currently exploring:

SystemVerilog 🛠️ Functional Verification

RTL Design 🧩 Finite State Machines

FPGA Projects using Vivado & Intel Quartus

UVM Basics & Testbench Architectures

EDA Toolchains and ASIC Workflows


💡 I believe in learning by building, and this profile is my digital lab where I publish what I experiment with — from simulation testbenches to real synthesis-ready modules.


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🔍 Explore my repositories:

📘 Educational Projects: Well-commented code & diagrams

🔬 Lab-style Experiments: Built from scratch, tested with testbenches

📊 Presentations & Slides: Designed for quick learning

🤝 Collaborative Repos: Open to pull requests and contributions!



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🚀 Let's Connect & Grow Together

🔗 Linkedin:-https://www.linkedin.com/in/praveen-kumar-podalakur-78b628287?utm_source=share&utm_campaign=share_via&utm_content=profile&utm_medium=android_app

📫 Drop issues or ideas in the repos — I’m always open to feedback & collab!