Search results

Inconsistency between Verilog Maths and Python Fixed-Point Model

bugSomething isn't workingSomething isn't working

Status: Open.

#167 In projf/projf-explore;

· WillGreen opened on Jun 27, 2023

Support SPRAM Framebuffer

enhancementNew feature or requestNew feature or request

Status: Open.

#133 In projf/projf-explore;

· WillGreen opened on Jan 3, 2023

UART echo's back half the input

bugSomething isn't workingSomething isn't working

Status: Open.

#131 In projf/projf-explore;

· eliquinox opened on Nov 27, 2022

Remove Old Clock Gen Modules

enhancementNew feature or requestNew feature or request

Status: Open.

#123 In projf/projf-explore;

· WillGreen opened on Oct 23, 2022

Colour Index Latency Correction with bitmap_addr

bugSomething isn't workingSomething isn't working

Status: Open.

#115 In projf/projf-explore;

· WillGreen opened on Sep 17, 2022

Sub-Pixel Drawing Precision

enhancementNew feature or requestNew feature or request

Status: Open.

#113 In projf/projf-explore;

· WillGreen opened on Sep 10, 2022

Shared Triangle Edges

enhancementNew feature or requestNew feature or request

Status: Open.

#112 In projf/projf-explore;

· WillGreen opened on Sep 10, 2022

Triangle outline and fill not congruent

bugSomething isn't workingSomething isn't working

Status: Open.

#111 In projf/projf-explore;

· WillGreen opened on Sep 9, 2022

Verilator/SDL Screen Array Unchecked (C++)

bugSomething isn't workingSomething isn't working

Status: Open.

#90 In projf/projf-explore;

· WillGreen opened on Feb 7, 2022