Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL
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Jun 20, 2025 - Verilog
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testbench-verification
Here are 5 public repositories matching this topic...
RTL code of an 8-bit CPU designed in Verilog.
personal-project learning-by-doing computer-architecture verilog-hdl cpu-architecture rtl-design testbench-verification
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Aug 12, 2024 - Verilog
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
verilog uart serial-communication data-transmission rtl-design testbench-verification serial-communication-protocol asynchronous-transmission
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Dec 19, 2023 - Verilog
This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7
verilog mux multiplexer testbench digital-design xilinx-vivado structural-design testbench-verification behavioural-simulation behavioural-design
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May 28, 2025 - Verilog
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