GitHub - buhman/cpu: FPGA-synthesizable RISC-V implementation

buhman / cpu Public

FPGA-synthesizable RISC-V implementation

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Name		Name	Last commit message	Last commit date
Latest commit History 38 Commits
sim		sim
tb		tb
test		test
.gitignore		.gitignore
Makefile		Makefile
btb.v		btb.v
control.v		control.v
control.vh		control.vh
cpu.v		cpu.v
csr_reg.v		csr_reg.v
csr_reg.vh		csr_reg.vh
decode.v		decode.v
dmem.v		dmem.v
dmem_decode.v		dmem_decode.v
dmem_encdec.vh		dmem_encdec.vh
dmem_encode.v		dmem_encode.v
execute.v		execute.v
execute.vh		execute.vh
fetch.v		fetch.v
hazard.v		hazard.v
imem.v		imem.v
int_alu.v		int_alu.v
int_alu.vh		int_alu.vh
int_reg.v		int_reg.v
jump.v		jump.v
jump.vh		jump.vh
mem_branch.v		mem_branch.v
sigma.pcf		sigma.pcf
state.vh		state.vh
top.v		top.v
writeback.v		writeback.v
writeback.vh		writeback.vh

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