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Inconsistent result on riscv64 with fmul, compared to other architectures #10976

@akldc

Description

@akldc

.clif Test Case

test optimize    
    set opt_level=none
    set preserve_frame_pointers=true
    set enable_multi_ret_implicit_sret=true
            

function %main() -> f64x2 fast {
    const0 = 0x66dcb93ce18195cd25ba9b1858b0b8d5
    
block0:
    v14 = vconst.f64x2 const0
    v16 = bor_not v14, v14  ; v14 = const0, v14 = const0
    v80 = fmul.f64x2 v14, v16  ; v14 = const0
    return v80
}

; print: %main()

Result

Run this test case on four architectures.

[x86    ] %main() -> 0xffffffffffffffffffffffffffffffff
[aarch64] %main() -> 0xffffffffffffffffffffffffffffffff
[riscv64] %main() -> 0x7ff80000000000007ff8000000000000
[s390x  ] %main() -> 0xffffffffffffffffffffffffffffffff

The result on riscv64 differs from the other architectures.

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    bugIncorrect behavior in the current implementation that needs fixingcranelift:area:riscv64Issues related to the RISC-V 64 backend.fuzz-bugBugs found by a fuzzer

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