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This was added in #5366 but upon reflection I don't think that it's necessary as almost all of the definitions reuse the temporary register as the destination register as well. The original motivation looks like it's relate to the SSA-ness of instructions but I believe the way it's generated it's all SSA-valid, so this commit removes the temp allocation function and uses rd, the destination register, unconditionally instead.

This was added in bytecodealliance#5366 but upon reflection I don't think that it's
necessary as almost all of the definitions reuse the temporary register
as the destination register as well. The original motivation looks like
it's relate to the SSA-ness of instructions but I believe the way it's
generated it's all SSA-valid, so this commit removes the temp allocation
function and uses `rd`, the destination register, unconditionally
instead.
@alexcrichton alexcrichton requested a review from a team as a code owner June 10, 2025 15:48
@alexcrichton alexcrichton requested review from fitzgen and removed request for a team June 10, 2025 15:48
@fitzgen fitzgen added this pull request to the merge queue Jun 10, 2025
Merged via the queue into bytecodealliance:main with commit 5818cec Jun 10, 2025
41 checks passed
@alexcrichton alexcrichton deleted the aarch64-remove-closure-from-load-constant branch June 10, 2025 19:05
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2 participants