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| 1 | +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Muhammed Efe Cetin <efectn@protonmail.com> |
| 3 | +Date: Sat, 26 Apr 2025 15:45:44 +0300 |
| 4 | +Subject: add sata dts and defconfig for OPi5 |
| 5 | + |
| 6 | +--- |
| 7 | + arch/arm/dts/rk3588s-orangepi-5-sata-u-boot.dtsi | 16 ++ |
| 8 | + configs/orangepi-5-sata-rk3588s_defconfig | 93 ++++++++++ |
| 9 | + dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-sata.dts | 33 ++++ |
| 10 | + 3 files changed, 142 insertions(+) |
| 11 | + |
| 12 | +diff --git a/arch/arm/dts/rk3588s-orangepi-5-sata-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-sata-u-boot.dtsi |
| 13 | +new file mode 100644 |
| 14 | +index 000000000000..111111111111 |
| 15 | +--- /dev/null |
| 16 | ++++ b/arch/arm/dts/rk3588s-orangepi-5-sata-u-boot.dtsi |
| 17 | +@@ -0,0 +1,16 @@ |
| 18 | ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 19 | ++ |
| 20 | ++#include "rk3588s-u-boot.dtsi" |
| 21 | ++#include "rk3588s-orangepi-5-u-boot.dtsi" |
| 22 | ++ |
| 23 | ++/ { |
| 24 | ++ chosen { |
| 25 | ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc; |
| 26 | ++ }; |
| 27 | ++}; |
| 28 | ++ |
| 29 | ++&binman { |
| 30 | ++ simple-bin-spi { |
| 31 | ++ filename = "u-boot-rockchip-spi-sata.bin"; |
| 32 | ++ }; |
| 33 | ++}; |
| 34 | +\ No newline at end of file |
| 35 | +diff --git a/configs/orangepi-5-sata-rk3588s_defconfig b/configs/orangepi-5-sata-rk3588s_defconfig |
| 36 | +new file mode 100644 |
| 37 | +index 000000000000..111111111111 |
| 38 | +--- /dev/null |
| 39 | ++++ b/configs/orangepi-5-sata-rk3588s_defconfig |
| 40 | +@@ -0,0 +1,93 @@ |
| 41 | ++CONFIG_ARM=y |
| 42 | ++CONFIG_SKIP_LOWLEVEL_INIT=y |
| 43 | ++CONFIG_COUNTER_FREQUENCY=24000000 |
| 44 | ++CONFIG_ARCH_ROCKCHIP=y |
| 45 | ++CONFIG_SF_DEFAULT_SPEED=24000000 |
| 46 | ++CONFIG_SF_DEFAULT_MODE=0x2000 |
| 47 | ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-orangepi-5-sata" |
| 48 | ++CONFIG_ROCKCHIP_RK3588=y |
| 49 | ++CONFIG_ROCKCHIP_SPI_IMAGE=y |
| 50 | ++CONFIG_SPL_SERIAL=y |
| 51 | ++CONFIG_TARGET_EVB_RK3588=y |
| 52 | ++CONFIG_SYS_LOAD_ADDR=0xc00800 |
| 53 | ++CONFIG_SF_DEFAULT_BUS=5 |
| 54 | ++CONFIG_DEBUG_UART_BASE=0xFEB50000 |
| 55 | ++CONFIG_DEBUG_UART_CLOCK=24000000 |
| 56 | ++CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 57 | ++CONFIG_SPL_SPI=y |
| 58 | ++CONFIG_PCI=y |
| 59 | ++CONFIG_DEBUG_UART=y |
| 60 | ++CONFIG_AHCI=y |
| 61 | ++CONFIG_FIT=y |
| 62 | ++CONFIG_FIT_VERBOSE=y |
| 63 | ++CONFIG_SPL_FIT_SIGNATURE=y |
| 64 | ++CONFIG_SPL_LOAD_FIT=y |
| 65 | ++CONFIG_LEGACY_IMAGE_FORMAT=y |
| 66 | ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5-sata.dtb" |
| 67 | ++# CONFIG_DISPLAY_CPUINFO is not set |
| 68 | ++CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 69 | ++CONFIG_SPL_MAX_SIZE=0x40000 |
| 70 | ++CONFIG_SPL_PAD_TO=0x7f8000 |
| 71 | ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 72 | ++CONFIG_SPL_SPI_LOAD=y |
| 73 | ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 |
| 74 | ++CONFIG_SPL_ATF=y |
| 75 | ++CONFIG_CMD_GPIO=y |
| 76 | ++CONFIG_CMD_GPT=y |
| 77 | ++CONFIG_CMD_I2C=y |
| 78 | ++CONFIG_CMD_MMC=y |
| 79 | ++CONFIG_CMD_PCI=y |
| 80 | ++CONFIG_CMD_USB=y |
| 81 | ++# CONFIG_CMD_SETEXPR is not set |
| 82 | ++CONFIG_CMD_REGULATOR=y |
| 83 | ++# CONFIG_SPL_DOS_PARTITION is not set |
| 84 | ++CONFIG_SPL_OF_CONTROL=y |
| 85 | ++CONFIG_OF_LIVE=y |
| 86 | ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 87 | ++CONFIG_SPL_DM_SEQ_ALIAS=y |
| 88 | ++CONFIG_SPL_REGMAP=y |
| 89 | ++CONFIG_SPL_SYSCON=y |
| 90 | ++CONFIG_AHCI_PCI=y |
| 91 | ++CONFIG_DWC_AHCI=y |
| 92 | ++CONFIG_SPL_CLK=y |
| 93 | ++CONFIG_ROCKCHIP_GPIO=y |
| 94 | ++CONFIG_SYS_I2C_ROCKCHIP=y |
| 95 | ++CONFIG_MISC=y |
| 96 | ++CONFIG_SUPPORT_EMMC_RPMB=y |
| 97 | ++CONFIG_MMC_DW=y |
| 98 | ++CONFIG_MMC_DW_ROCKCHIP=y |
| 99 | ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y |
| 100 | ++CONFIG_SPI_FLASH_XMC=y |
| 101 | ++CONFIG_PHY_MOTORCOMM=y |
| 102 | ++CONFIG_DWC_ETH_QOS=y |
| 103 | ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y |
| 104 | ++CONFIG_NVME_PCI=y |
| 105 | ++CONFIG_PCIE_DW_ROCKCHIP=y |
| 106 | ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y |
| 107 | ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y |
| 108 | ++CONFIG_PHY_ROCKCHIP_USBDP=y |
| 109 | ++CONFIG_SPL_PINCTRL=y |
| 110 | ++CONFIG_PWM_ROCKCHIP=y |
| 111 | ++CONFIG_SPL_RAM=y |
| 112 | ++CONFIG_SCSI=y |
| 113 | ++CONFIG_BAUDRATE=1500000 |
| 114 | ++CONFIG_DEBUG_UART_SHIFT=2 |
| 115 | ++CONFIG_SYS_NS16550_MEM32=y |
| 116 | ++CONFIG_ROCKCHIP_SFC=y |
| 117 | ++CONFIG_SYSRESET=y |
| 118 | ++CONFIG_USB=y |
| 119 | ++CONFIG_USB_XHCI_HCD=y |
| 120 | ++CONFIG_USB_EHCI_HCD=y |
| 121 | ++CONFIG_USB_EHCI_GENERIC=y |
| 122 | ++CONFIG_USB_OHCI_HCD=y |
| 123 | ++CONFIG_USB_OHCI_GENERIC=y |
| 124 | ++CONFIG_USB_DWC3=y |
| 125 | ++CONFIG_USB_DWC3_GENERIC=y |
| 126 | ++CONFIG_ERRNO_STR=y |
| 127 | ++CONFIG_AHCI=y |
| 128 | ++CONFIG_CMD_SCSI=y |
| 129 | ++CONFIG_DM_SCSI=y |
| 130 | ++CONFIG_DWC_AHCI=y |
| 131 | ++CONFIG_LIBATA=y |
| 132 | ++CONFIG_SCSI_AHCI=y |
| 133 | ++CONFIG_SCSI=y |
| 134 | +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-sata.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-sata.dts |
| 135 | +new file mode 100644 |
| 136 | +index 000000000000..111111111111 |
| 137 | +--- /dev/null |
| 138 | ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5-sata.dts |
| 139 | +@@ -0,0 +1,33 @@ |
| 140 | ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 141 | ++ |
| 142 | ++/dts-v1/; |
| 143 | ++ |
| 144 | ++#include "rk3588s-orangepi-5.dtsi" |
| 145 | ++#include <dt-bindings/pinctrl/rockchip.h> |
| 146 | ++#include <dt-bindings/gpio/gpio.h> |
| 147 | ++ |
| 148 | ++/ { |
| 149 | ++ model = "Xunlong Orange Pi 5 (Sata)"; |
| 150 | ++ compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; |
| 151 | ++}; |
| 152 | ++ |
| 153 | ++&sata0 { |
| 154 | ++ pinctrl-names = "default"; |
| 155 | ++ pinctrl-0 = <&sata_reset>; |
| 156 | ++ status = "okay"; |
| 157 | ++ |
| 158 | ++ phys = <&combphy0_ps PHY_TYPE_SATA>; |
| 159 | ++ phy-names = "sata-phy"; |
| 160 | ++}; |
| 161 | ++ |
| 162 | ++&sfc { |
| 163 | ++ status = "okay"; |
| 164 | ++}; |
| 165 | ++ |
| 166 | ++&pinctrl { |
| 167 | ++ sata { |
| 168 | ++ sata_reset: sata-reset { |
| 169 | ++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; |
| 170 | ++ }; |
| 171 | ++ }; |
| 172 | ++}; |
| 173 | +-- |
| 174 | +Armbian |
| 175 | + |
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