Inaccurate description of bit 7 in a P1 in paging-introduction

[ChocolateLoverRaj]

In the blog it says

must be 0 in P1 and P4, creates a 1 GiB page in P3, creates a 2 MiB page in P2

But in Intel® 64 and IA-32 Architectures Software Developer’s Manual > Volume 3 > 5.5.4
Linear-Address Translation with 4-Level Paging and 5-Level Paging > Table 5-20. Format of a Page-Table Entry that Maps a 4-KByte Page

For bit 7 it says

7 (PAT) | Indirectly determines the memory type used to access the 4-KByte page referenced by this entry (see Section 5.9.2)

And idk what PAT is, but after looking at the page tables created by the Limine bootloader and the documentation, i'm pretty sure that bit 7 does not have to be 0 in P1.