arch: add MIPS architecture support

MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.

This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

Author: frantony

CODEOWNERS

@@ -25,6 +25,7 @@
 /arch/arm64/core/cortex_r/                @povergoing
 /arch/arm64/core/xen/                     @lorc @firscity
 /arch/common/                             @ioannisg @andyross
+/arch/mips/                               @frantony
 /soc/arc/snps_*/                          @abrodkin @ruuddw @evgeniy-paltsev
 /soc/nios2/                               @nashif
 /soc/arm/                                 @MaureenHelm @galak @ioannisg
@@ -533,6 +534,7 @@
 /include/arch/arm64/                      @carlocaione
 /include/arch/arm64/cortex_r/             @povergoing
 /include/arch/arm/aarch32/irq.h           @carlocaione
+/include/arch/mips/                       @frantony
 /include/arch/nios2/                      @nashif
 /include/arch/nios2/arch.h                @nashif
 /include/arch/posix/                      @aescolar @daor-oti

arch/Kconfig

@@ -49,6 +49,14 @@ config ARM64
 	help
 	  ARM64 (AArch64) architecture
 
+config MIPS
+	bool
+	select ARCH_IS_SET
+	select ATOMIC_OPERATIONS_C
+	select HAS_DTS
+	help
+	  MIPS architecture
+
 config SPARC
 	bool
 	select ARCH_IS_SET

arch/mips/CMakeLists.txt

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+#
+# based on arch/riscv/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_BIG_ENDIAN)
+	set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-bigmips")
+else()
+	set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-littlemips")
+endif()
+
+add_subdirectory(core)
+zephyr_include_directories(include)

arch/mips/Kconfig

@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+#
+# based on arch/riscv/Kconfig
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menu "MIPS Options"
+	depends on MIPS
+
+config ARCH
+	string
+	default "mips"
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config GEN_SW_ISR_TABLE
+	default y
+
+config NUM_IRQS
+	int
+
+# Bump the kernel default stack size values.
+config MAIN_STACK_SIZE
+	default 4096 if COVERAGE_GCOV
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024
+
+config ISR_STACK_SIZE
+	default 4096
+
+config TEST_EXTRA_STACKSIZE
+	default 4096 if COVERAGE_GCOV
+	default 2048
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 4096
+
+config CMSIS_THREAD_MAX_STACK_SIZE
+	default 2048
+
+config CMSIS_V2_THREAD_MAX_STACK_SIZE
+	default 2048
+
+config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
+	default 2048
+
+config IPM_CONSOLE_STACK_SIZE
+	default 4096 if COVERAGE
+	default 1024
+
+endmenu

arch/mips/core/CMakeLists.txt

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(
+  cpu_idle.c
+  fatal.c
+  irq_manage.c
+  isr.S
+  prep_c.c
+  reset.S
+  swap.S
+  thread.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)

arch/mips/core/cpu_idle.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <irq.h>
+
+#include <tracing/tracing.h>
+
+static ALWAYS_INLINE void mips_idle(unsigned int key)
+{
+	sys_trace_idle();
+
+	/* unlock interrupts */
+	irq_unlock(key);
+
+	/* wait for interrupt */
+	__asm__ volatile("wait");
+}
+
+void arch_cpu_idle(void)
+{
+	mips_idle(1);
+}
+
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	mips_idle(key);
+}

arch/mips/core/fatal.c

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <sys/printk.h>
+#include <logging/log.h>
+LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
+
+FUNC_NORETURN void z_mips_fatal_error(unsigned int reason,
+					  const z_arch_esf_t *esf)
+{
+	if (esf != NULL) {
+		printk("$ 0   :         (ze) %08lx(at) %08lx(v0) %08lx(v1)\n",
+			esf->at, esf->v0, esf->v1);
+		printk("$ 4   : %08lx(a0) %08lx(a1) %08lx(a2) %08lx(a3)\n",
+			esf->a0, esf->a1, esf->a2, esf->a3);
+		printk("$ 8   : %08lx(t0) %08lx(t1) %08lx(t2) %08lx(t3)\n",
+			esf->t0, esf->t1, esf->t2, esf->t3);
+		printk("$12   : %08lx(t4) %08lx(t5) %08lx(t6) %08lx(t7)\n",
+			esf->t4, esf->t5, esf->t6, esf->t7);
+		printk("...\n");
+		printk("$24   : %08lx(t8) %08lx(t9)\n",
+			esf->t8, esf->t9);
+		printk("$28   : %08lx(gp)         (sp)         (s8) %08lx(ra)\n",
+			esf->gp, esf->ra);
+
+		printk("EPC   : %08lx\n", esf->epc);
+
+		printk("Status: %08lx\n", esf->status);
+		printk("Cause : %08lx\n", esf->cause);
+		printk("BadVA : %08lx\n", esf->badvaddr);
+	}
+
+	z_fatal_error(reason, esf);
+	CODE_UNREACHABLE;
+}
+
+static char *cause_str(ulong_t cause)
+{
+	switch (cause) {
+	case 0:
+		return "interrupt pending";
+	case 1:
+		return "TLB modified";
+	case 2:
+		return "TLB miss on load or ifetch";
+	case 3:
+		return "TLB miss on store";
+	case 4:
+		return "address error on load or ifetch";
+	case 5:
+		return "address error on store";
+	case 6:
+		return "bus error on ifetch";
+	case 7:
+		return "bus error on load or store";
+	case 8:
+		return "system call";
+	case 9:
+		return "breakpoint";
+	case 10:
+		return "reserved instruction";
+	case 11:
+		return "coprocessor unusable";
+	case 12:
+		return "arithmetic overflow";
+	case 13:
+		return "trap instruction";
+	case 14:
+		return "virtual coherency instruction";
+	case 15:
+		return "floating point";
+	case 16:
+		return "iwatch";
+	case 23:
+		return "dwatch";
+	case 31:
+		return "virtual coherency data";
+	default:
+		return "unknown";
+	}
+}
+
+void _Fault(z_arch_esf_t *esf)
+{
+	ulong_t cause;
+
+	cause = (read_c0_cause() & CAUSE_EXP_MASK) >> CAUSE_EXP_SHIFT;
+
+	LOG_ERR("");
+	LOG_ERR(" cause: %ld, %s", cause, cause_str(cause));
+
+	z_mips_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+}

arch/mips/core/irq_manage.c

@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * based on arch/nios2/core/irq_manage.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <kswap.h>
+#include <logging/log.h>
+LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
+
+
+uint32_t mips_cp0_status_int_mask;
+
+
+FUNC_NORETURN void z_irq_spurious(const void *unused)
+{
+	ulong_t cause;
+
+	ARG_UNUSED(unused);
+	cause = (read_c0_cause() & CAUSE_EXP_MASK) >> CAUSE_EXP_SHIFT;
+
+	LOG_ERR("Spurious interrupt detected! CAUSE: %ld", cause);
+
+	z_mips_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
+}
+
+void arch_irq_enable(unsigned int irq)
+{
+	unsigned int key;
+	uint32_t irq_mask;
+
+	key = irq_lock();
+
+	irq_mask = ST0_IP0 << irq;
+	mips_cp0_status_int_mask |= irq_mask;
+	write_c0_status(read_c0_status() | irq_mask);
+
+	irq_unlock(key);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	unsigned int key;
+	uint32_t irq_mask;
+
+	key = irq_lock();
+
+	irq_mask = ST0_IP0 << irq;
+	mips_cp0_status_int_mask &= ~irq_mask;
+	write_c0_status(read_c0_status() & ~irq_mask);
+
+	irq_unlock(key);
+};
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	return read_c0_status() & (ST0_IP0 << irq);
+}
+
+void z_mips_enter_irq(uint32_t ipending)
+{
+	_current_cpu->nested++;
+
+#ifdef CONFIG_IRQ_OFFLOAD
+	z_irq_do_offload();
+#endif
+
+	while (ipending) {
+		int index;
+		struct _isr_table_entry *ite;
+
+		if (IS_ENABLED(CONFIG_TRACING_ISR))
+			sys_trace_isr_enter();
+
+		index = find_lsb_set(ipending) - 1;
+		ipending &= ~BIT(index);
+
+		ite = &_sw_isr_table[index];
+
+		ite->isr(ite->arg);
+
+		if (IS_ENABLED(CONFIG_TRACING_ISR))
+			sys_trace_isr_exit();
+	}
+
+	_current_cpu->nested--;
+
+	if (IS_ENABLED(CONFIG_STACK_SENTINEL))
+		z_check_stack_sentinel();
+}
+
+#ifdef CONFIG_DYNAMIC_INTERRUPTS
+int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+			     void (*routine)(const void *parameter),
+			     const void *parameter, uint32_t flags)
+{
+	ARG_UNUSED(flags);
+	ARG_UNUSED(priority);
+
+	z_isr_install(irq, routine, parameter);
+	return irq;
+}
+#endif /* CONFIG_DYNAMIC_INTERRUPTS */