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Copy pathLowerMDSharedSimd128.cpp
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LowerMDSharedSimd128.cpp
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//-------------------------------------------------------------------------------------------------------
// Copyright (C) Microsoft Corporation and contributors. All rights reserved.
// Licensed under the MIT license. See LICENSE.txt file in the project root for full license information.
//-------------------------------------------------------------------------------------------------------
#include "Backend.h"
static IR::Instr* removeInstr(IR::Instr* instr);
#ifdef ENABLE_WASM_SIMD
static IR::Instr* removeInstr(IR::Instr* instr)
{
IR::Instr* prevInstr;
prevInstr = instr->m_prev;
instr->Remove();
return prevInstr;
}
#define GET_SIMDOPCODE(irOpcode) m_simd128OpCodesMap[(uint32)(irOpcode - Js::OpCode::Simd128_Start)]
#define SET_SIMDOPCODE(irOpcode, mdOpcode) \
Assert((uint32)m_simd128OpCodesMap[(uint32)(Js::OpCode::irOpcode - Js::OpCode::Simd128_Start)] == 0);\
Assert(Js::OpCode::mdOpcode > Js::OpCode::MDStart);\
m_simd128OpCodesMap[(uint32)(Js::OpCode::irOpcode - Js::OpCode::Simd128_Start)] = Js::OpCode::mdOpcode;
IR::Instr* LowererMD::Simd128Instruction(IR::Instr *instr)
{
// Currently only handles type-specialized/asm.js opcodes
if (!instr->GetDst())
{
// SIMD ops always have DST in asmjs
Assert(!instr->m_func->GetJITFunctionBody()->IsAsmJsMode());
// unused result. Do nothing.
IR::Instr * pInstr = instr->m_prev;
instr->Remove();
return pInstr;
}
if (Simd128TryLowerMappedInstruction(instr))
{
return instr->m_prev;
}
return Simd128LowerUnMappedInstruction(instr);
}
bool LowererMD::Simd128TryLowerMappedInstruction(IR::Instr *instr)
{
bool legalize = true;
Js::OpCode opcode = GET_SIMDOPCODE(instr->m_opcode);
if ((uint32)opcode == 0)
return false;
Assert(instr->GetDst() && instr->GetDst()->IsRegOpnd() && instr->GetDst()->IsSimd128() || instr->GetDst()->GetType() == TyInt32);
Assert(instr->GetSrc1() && instr->GetSrc1()->IsRegOpnd() && instr->GetSrc1()->IsSimd128());
Assert(!instr->GetSrc2() || (((instr->GetSrc2()->IsRegOpnd() && instr->GetSrc2()->IsSimd128()) || (instr->GetSrc2()->IsIntConstOpnd() && instr->GetSrc2()->GetType() == TyInt8))));
switch (instr->m_opcode)
{
case Js::OpCode::Simd128_Abs_F4:
Assert(opcode == Js::OpCode::ANDPS);
instr->SetSrc2(IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AbsMaskF4Addr(), instr->GetSrc1()->GetType(), m_func));
break;
case Js::OpCode::Simd128_Abs_D2:
Assert(opcode == Js::OpCode::ANDPD);
instr->SetSrc2(IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AbsMaskD2Addr(), instr->GetSrc1()->GetType(), m_func));
break;
case Js::OpCode::Simd128_Neg_F4:
Assert(opcode == Js::OpCode::XORPS);
instr->SetSrc2(IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86NegMaskF4Addr(), instr->GetSrc1()->GetType(), m_func));
break;
case Js::OpCode::Simd128_Neg_D2:
Assert(opcode == Js::OpCode::XORPS);
instr->SetSrc2(IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86NegMaskD2Addr(), instr->GetSrc1()->GetType(), m_func));
break;
case Js::OpCode::Simd128_Not_I4:
case Js::OpCode::Simd128_Not_I16:
case Js::OpCode::Simd128_Not_I8:
case Js::OpCode::Simd128_Not_U4:
case Js::OpCode::Simd128_Not_U8:
case Js::OpCode::Simd128_Not_U16:
case Js::OpCode::Simd128_Not_B4:
case Js::OpCode::Simd128_Not_B8:
case Js::OpCode::Simd128_Not_B16:
Assert(opcode == Js::OpCode::XORPS);
instr->SetSrc2(IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AllNegOnesAddr(), instr->GetSrc1()->GetType(), m_func));
break;
case Js::OpCode::Simd128_Gt_F4:
case Js::OpCode::Simd128_Gt_D2:
case Js::OpCode::Simd128_GtEq_F4:
case Js::OpCode::Simd128_GtEq_D2:
case Js::OpCode::Simd128_Lt_I4:
case Js::OpCode::Simd128_Lt_I8:
case Js::OpCode::Simd128_Lt_I16:
{
Assert(opcode == Js::OpCode::CMPLTPS || opcode == Js::OpCode::CMPLTPD || opcode == Js::OpCode::CMPLEPS
|| opcode == Js::OpCode::CMPLEPD || opcode == Js::OpCode::PCMPGTD || opcode == Js::OpCode::PCMPGTB
|| opcode == Js::OpCode::PCMPGTW );
// swap operands
auto *src1 = instr->UnlinkSrc1();
auto *src2 = instr->UnlinkSrc2();
instr->SetSrc1(src2);
instr->SetSrc2(src1);
break;
}
}
instr->m_opcode = opcode;
if (legalize)
{
//MakeDstEquSrc1(instr);
Legalize(instr);
}
return true;
}
IR::MemRefOpnd *
LowererMD::LoadSimdHelperArgument(IR::Instr * instr, uint8 index)
{
//the most reliable way to pass a simd value on x86/x64 win/lnx across calls
//is to pass a pointer to a SIMD value in the simd temporary area.
//otherwise we have to use __m128 and msvc intrinsics which may or may not be the same across
//MSVC and Clang
IR::MemRefOpnd* srcMemRef = IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetSimdTempAreaAddr(index), TySimd128F4, m_func);
IR::AddrOpnd* argAddress = IR::AddrOpnd::New(m_func->GetThreadContextInfo()->GetSimdTempAreaAddr(index), IR::AddrOpndKindDynamicMisc, m_func, true /* doesn't come from a user */);
LoadHelperArgument(instr, argAddress);
return srcMemRef;
}
IR::Instr* LowererMD::Simd128LowerUnMappedInstruction(IR::Instr *instr)
{
switch (instr->m_opcode)
{
case Js::OpCode::Simd128_LdC:
return Simd128LoadConst(instr);
#ifdef ENABLE_SIMD
case Js::OpCode::Simd128_FloatsToF4:
case Js::OpCode::Simd128_IntsToI4:
case Js::OpCode::Simd128_IntsToU4:
case Js::OpCode::Simd128_IntsToB4:
return Simd128LowerConstructor_4(instr);
case Js::OpCode::Simd128_IntsToI8:
case Js::OpCode::Simd128_IntsToU8:
case Js::OpCode::Simd128_IntsToB8:
return Simd128LowerConstructor_8(instr);
case Js::OpCode::Simd128_IntsToI16:
case Js::OpCode::Simd128_IntsToU16:
case Js::OpCode::Simd128_IntsToB16:
return Simd128LowerConstructor_16(instr);
case Js::OpCode::Simd128_Rcp_F4:
//case Js::OpCode::Simd128_Rcp_D2:
return Simd128LowerRcp(instr);
//SQRT
case Js::OpCode::Simd128_RcpSqrt_F4:
//case Js::OpCode::Simd128_RcpSqrt_D2:
return Simd128LowerRcpSqrt(instr);
case Js::OpCode::Simd128_Select_F4:
case Js::OpCode::Simd128_Select_I4:
//case Js::OpCode::Simd128_Select_D2:
case Js::OpCode::Simd128_Select_I8:
case Js::OpCode::Simd128_Select_I16:
case Js::OpCode::Simd128_Select_U4:
case Js::OpCode::Simd128_Select_U8:
case Js::OpCode::Simd128_Select_U16:
return Simd128LowerSelect(instr);
#endif
#if 0
case Js::OpCode::Simd128_DoublesToD2:
return Simd128LowerConstructor_2(instr);
#endif // 0
case Js::OpCode::Simd128_ExtractLane_I2:
case Js::OpCode::Simd128_ExtractLane_I4:
case Js::OpCode::Simd128_ExtractLane_I8:
case Js::OpCode::Simd128_ExtractLane_I16:
case Js::OpCode::Simd128_ExtractLane_U4:
case Js::OpCode::Simd128_ExtractLane_U8:
case Js::OpCode::Simd128_ExtractLane_U16:
case Js::OpCode::Simd128_ExtractLane_B4:
case Js::OpCode::Simd128_ExtractLane_B8:
case Js::OpCode::Simd128_ExtractLane_B16:
case Js::OpCode::Simd128_ExtractLane_F4:
return Simd128LowerLdLane(instr);
case Js::OpCode::Simd128_ReplaceLane_I2:
case Js::OpCode::Simd128_ReplaceLane_D2:
return SIMD128LowerReplaceLane_2(instr);
case Js::OpCode::Simd128_ReplaceLane_I4:
case Js::OpCode::Simd128_ReplaceLane_F4:
case Js::OpCode::Simd128_ReplaceLane_U4:
case Js::OpCode::Simd128_ReplaceLane_B4:
return SIMD128LowerReplaceLane_4(instr);
case Js::OpCode::Simd128_ReplaceLane_I8:
case Js::OpCode::Simd128_ReplaceLane_U8:
case Js::OpCode::Simd128_ReplaceLane_B8:
return SIMD128LowerReplaceLane_8(instr);
case Js::OpCode::Simd128_ReplaceLane_I16:
case Js::OpCode::Simd128_ReplaceLane_U16:
case Js::OpCode::Simd128_ReplaceLane_B16:
return SIMD128LowerReplaceLane_16(instr);
case Js::OpCode::Simd128_Splat_F4:
case Js::OpCode::Simd128_Splat_I4:
case Js::OpCode::Simd128_Splat_I2:
case Js::OpCode::Simd128_Splat_D2:
case Js::OpCode::Simd128_Splat_I8:
case Js::OpCode::Simd128_Splat_I16:
case Js::OpCode::Simd128_Splat_U4:
case Js::OpCode::Simd128_Splat_U8:
case Js::OpCode::Simd128_Splat_U16:
case Js::OpCode::Simd128_Splat_B4:
case Js::OpCode::Simd128_Splat_B8:
case Js::OpCode::Simd128_Splat_B16:
return Simd128LowerSplat(instr);
case Js::OpCode::Simd128_Sqrt_F4:
//case Js::OpCode::Simd128_Sqrt_D2:
return Simd128LowerSqrt(instr);
case Js::OpCode::Simd128_Neg_I4:
case Js::OpCode::Simd128_Neg_I8:
case Js::OpCode::Simd128_Neg_I16:
case Js::OpCode::Simd128_Neg_U4:
case Js::OpCode::Simd128_Neg_U8:
case Js::OpCode::Simd128_Neg_U16:
return Simd128LowerNeg(instr);
case Js::OpCode::Simd128_Mul_I4:
case Js::OpCode::Simd128_Mul_U4:
return Simd128LowerMulI4(instr);
case Js::OpCode::Simd128_Mul_I16:
case Js::OpCode::Simd128_Mul_U16:
return Simd128LowerMulI16(instr);
case Js::OpCode::Simd128_ShRtByScalar_I4:
case Js::OpCode::Simd128_ShLtByScalar_I4:
case Js::OpCode::Simd128_ShRtByScalar_I8:
case Js::OpCode::Simd128_ShLtByScalar_I8:
case Js::OpCode::Simd128_ShLtByScalar_I16:
case Js::OpCode::Simd128_ShRtByScalar_I16:
case Js::OpCode::Simd128_ShRtByScalar_U4:
case Js::OpCode::Simd128_ShLtByScalar_U4:
case Js::OpCode::Simd128_ShRtByScalar_U8:
case Js::OpCode::Simd128_ShLtByScalar_U8:
case Js::OpCode::Simd128_ShRtByScalar_U16:
case Js::OpCode::Simd128_ShLtByScalar_U16:
case Js::OpCode::Simd128_ShLtByScalar_I2:
case Js::OpCode::Simd128_ShRtByScalar_U2:
case Js::OpCode::Simd128_ShRtByScalar_I2:
return Simd128LowerShift(instr);
case Js::OpCode::Simd128_LdArr_I4:
case Js::OpCode::Simd128_LdArr_I8:
case Js::OpCode::Simd128_LdArr_I16:
case Js::OpCode::Simd128_LdArr_U4:
case Js::OpCode::Simd128_LdArr_U8:
case Js::OpCode::Simd128_LdArr_U16:
case Js::OpCode::Simd128_LdArr_F4:
//case Js::OpCode::Simd128_LdArr_D2:
case Js::OpCode::Simd128_LdArrConst_I4:
case Js::OpCode::Simd128_LdArrConst_I8:
case Js::OpCode::Simd128_LdArrConst_I16:
case Js::OpCode::Simd128_LdArrConst_U4:
case Js::OpCode::Simd128_LdArrConst_U8:
case Js::OpCode::Simd128_LdArrConst_U16:
case Js::OpCode::Simd128_LdArrConst_F4:
//case Js::OpCode::Simd128_LdArrConst_D2:
if (m_func->GetJITFunctionBody()->IsAsmJsMode())
{
// with bound checks
return Simd128AsmJsLowerLoadElem(instr);
}
else
{
// non-AsmJs, boundChecks are extracted from instr
return Simd128LowerLoadElem(instr);
}
case Js::OpCode::Simd128_StArr_I4:
case Js::OpCode::Simd128_StArr_I8:
case Js::OpCode::Simd128_StArr_I16:
case Js::OpCode::Simd128_StArr_U4:
case Js::OpCode::Simd128_StArr_U8:
case Js::OpCode::Simd128_StArr_U16:
case Js::OpCode::Simd128_StArr_F4:
//case Js::OpCode::Simd128_StArr_D2:
case Js::OpCode::Simd128_StArrConst_I4:
case Js::OpCode::Simd128_StArrConst_I8:
case Js::OpCode::Simd128_StArrConst_I16:
case Js::OpCode::Simd128_StArrConst_U4:
case Js::OpCode::Simd128_StArrConst_U8:
case Js::OpCode::Simd128_StArrConst_U16:
case Js::OpCode::Simd128_StArrConst_F4:
//case Js::OpCode::Simd128_StArrConst_D2:
if (m_func->GetJITFunctionBody()->IsAsmJsMode())
{
return Simd128AsmJsLowerStoreElem(instr);
}
else
{
return Simd128LowerStoreElem(instr);
}
case Js::OpCode::Simd128_Swizzle_U4:
case Js::OpCode::Simd128_Swizzle_I4:
case Js::OpCode::Simd128_Swizzle_F4:
//case Js::OpCode::Simd128_Swizzle_D2:
return Simd128LowerSwizzle_4(instr);
case Js::OpCode::Simd128_Shuffle_U4:
case Js::OpCode::Simd128_Shuffle_I4:
case Js::OpCode::Simd128_Shuffle_F4:
//case Js::OpCode::Simd128_Shuffle_D2:
return Simd128LowerShuffle_4(instr);
case Js::OpCode::Simd128_Swizzle_I8:
case Js::OpCode::Simd128_Swizzle_I16:
case Js::OpCode::Simd128_Swizzle_U8:
case Js::OpCode::Simd128_Swizzle_U16:
case Js::OpCode::Simd128_Shuffle_I8:
case Js::OpCode::Simd128_Shuffle_I16:
case Js::OpCode::Simd128_Shuffle_U8:
case Js::OpCode::Simd128_Shuffle_U16:
return Simd128LowerShuffle(instr);
case Js::OpCode::Simd128_FromUint32x4_F4:
return Simd128LowerFloat32x4FromUint32x4(instr);
case Js::OpCode::Simd128_FromFloat32x4_I4:
return Simd128LowerInt32x4FromFloat32x4(instr);
case Js::OpCode::Simd128_FromFloat32x4_U4:
return Simd128LowerUint32x4FromFloat32x4(instr);
case Js::OpCode::Simd128_FromInt64x2_D2:
return EmitSimdConversion(instr, IR::HelperSimd128ConvertSD2);
case Js::OpCode::Simd128_FromUint64x2_D2:
return EmitSimdConversion(instr, IR::HelperSimd128ConvertUD2);
case Js::OpCode::Simd128_FromFloat64x2_I2:
return EmitSimdConversion(instr, IR::HelperSimd128TruncateI2);
case Js::OpCode::Simd128_FromFloat64x2_U2:
return EmitSimdConversion(instr, IR::HelperSimd128TruncateU2);
case Js::OpCode::Simd128_Neq_I4:
case Js::OpCode::Simd128_Neq_I8:
case Js::OpCode::Simd128_Neq_I16:
case Js::OpCode::Simd128_Neq_U4:
case Js::OpCode::Simd128_Neq_U8:
case Js::OpCode::Simd128_Neq_U16:
return Simd128LowerNotEqual(instr);
case Js::OpCode::Simd128_Lt_U4:
case Js::OpCode::Simd128_Lt_U8:
case Js::OpCode::Simd128_Lt_U16:
case Js::OpCode::Simd128_GtEq_U4:
case Js::OpCode::Simd128_GtEq_U8:
case Js::OpCode::Simd128_GtEq_U16:
return Simd128LowerLessThan(instr);
case Js::OpCode::Simd128_LtEq_I4:
case Js::OpCode::Simd128_LtEq_I8:
case Js::OpCode::Simd128_LtEq_I16:
case Js::OpCode::Simd128_LtEq_U4:
case Js::OpCode::Simd128_LtEq_U8:
case Js::OpCode::Simd128_LtEq_U16:
case Js::OpCode::Simd128_Gt_U4:
case Js::OpCode::Simd128_Gt_U8:
case Js::OpCode::Simd128_Gt_U16:
return Simd128LowerLessThanOrEqual(instr);
case Js::OpCode::Simd128_GtEq_I4:
case Js::OpCode::Simd128_GtEq_I8:
case Js::OpCode::Simd128_GtEq_I16:
return Simd128LowerGreaterThanOrEqual(instr);
case Js::OpCode::Simd128_Min_F4:
case Js::OpCode::Simd128_Max_F4:
return Simd128LowerMinMax_F4(instr);
case Js::OpCode::Simd128_AnyTrue_B2:
case Js::OpCode::Simd128_AnyTrue_B4:
case Js::OpCode::Simd128_AnyTrue_B8:
case Js::OpCode::Simd128_AnyTrue_B16:
return Simd128LowerAnyTrue(instr);
case Js::OpCode::Simd128_AllTrue_B2:
case Js::OpCode::Simd128_AllTrue_B4:
case Js::OpCode::Simd128_AllTrue_B8:
case Js::OpCode::Simd128_AllTrue_B16:
return Simd128LowerAllTrue(instr);
case Js::OpCode::Simd128_BitSelect_I4:
return LowerSimd128BitSelect(instr);
default:
AssertMsg(UNREACHED, "Unsupported Simd128 instruction");
}
return nullptr;
}
IR::Instr* LowererMD::LowerSimd128BitSelect(IR::Instr* instr)
{
SList<IR::Opnd*> *args = Simd128GetExtendedArgs(instr);
IR::Opnd *dst = args->Pop();
IR::Opnd *src1 = args->Pop();
IR::Opnd *src2 = args->Pop();
IR::Opnd *mask = args->Pop();
IR::Instr* pInstr = IR::Instr::New(Js::OpCode::PXOR, dst, src1, src2, m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
instr->InsertBefore(IR::Instr::New(Js::OpCode::PAND, dst, dst, mask, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PXOR, dst, dst, src2, m_func));
return removeInstr(instr);
}
IR::Instr* LowererMD::Simd128LoadConst(IR::Instr* instr)
{
Assert(instr->GetDst() && instr->m_opcode == Js::OpCode::Simd128_LdC);
Assert(instr->GetDst()->IsSimd128());
Assert(instr->GetSrc1()->IsSimd128());
Assert(instr->GetSrc1()->IsSimd128ConstOpnd());
Assert(instr->GetSrc2() == nullptr);
AsmJsSIMDValue value = instr->GetSrc1()->AsSimd128ConstOpnd()->m_value;
// MOVUPS dst, [const]
void *pValue = NativeCodeDataNewNoFixup(this->m_func->GetNativeCodeDataAllocator(), SIMDType<DataDesc_LowererMD_Simd128LoadConst>, value);
IR::Opnd * simdRef;
if (!m_func->IsOOPJIT())
{
simdRef = IR::MemRefOpnd::New((void *)pValue, instr->GetDst()->GetType(), instr->m_func);
}
else
{
int offset = NativeCodeData::GetDataTotalOffset(pValue);
simdRef = IR::IndirOpnd::New(IR::RegOpnd::New(m_func->GetTopFunc()->GetNativeCodeDataSym(), TyVar, m_func), offset, instr->GetDst()->GetType(),
#if DBG
NativeCodeData::GetDataDescription(pValue, m_func->m_alloc),
#endif
m_func, true);
GetLowerer()->addToLiveOnBackEdgeSyms->Set(m_func->GetTopFunc()->GetNativeCodeDataSym()->m_id);
}
instr->ReplaceSrc1(simdRef);
instr->m_opcode = LowererMDArch::GetAssignOp(instr->GetDst()->GetType());
Legalize(instr);
return instr->m_prev;
}
IR::Instr* LowererMD::Simd128CanonicalizeToBools(IR::Instr* instr, const Js::OpCode &cmpOpcode, IR::Opnd& dstOpnd)
{
Assert(instr->m_opcode == Js::OpCode::Simd128_IntsToB4 || instr->m_opcode == Js::OpCode::Simd128_IntsToB8 || instr->m_opcode == Js::OpCode::Simd128_IntsToB16 ||
instr->m_opcode == Js::OpCode::Simd128_ReplaceLane_B4 || instr->m_opcode == Js::OpCode::Simd128_ReplaceLane_B8 || instr->m_opcode == Js::OpCode::Simd128_ReplaceLane_B16 ||
instr->m_opcode == Js::OpCode::Simd128_AnyTrue_B2 || instr->m_opcode == Js::OpCode::Simd128_AnyTrue_B4 || instr->m_opcode == Js::OpCode::Simd128_AnyTrue_B8 || instr->m_opcode == Js::OpCode::Simd128_AnyTrue_B16 ||
instr->m_opcode == Js::OpCode::Simd128_AllTrue_B2 || instr->m_opcode == Js::OpCode::Simd128_AllTrue_B4 || instr->m_opcode == Js::OpCode::Simd128_AllTrue_B8 || instr->m_opcode == Js::OpCode::Simd128_AllTrue_B16
);
IR::Instr *pInstr;
//dst = cmpOpcode dst, X86_ALL_ZEROS
pInstr = IR::Instr::New(cmpOpcode, &dstOpnd, &dstOpnd, IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AllZerosAddr(), TySimd128I4, m_func), m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
// dst = PANDN dst, X86_ALL_NEG_ONES
pInstr = IR::Instr::New(Js::OpCode::PANDN, &dstOpnd, &dstOpnd, IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AllNegOnesAddr(), TySimd128I4, m_func), m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
return instr;
}
IR::Instr* LowererMD::EmitSimdConversion(IR::Instr *instr, IR::JnHelperMethod helper)
{
IR::MemRefOpnd* srcMemRef = LoadSimdHelperArgument(instr, 0);
IR::MemRefOpnd* dstMemRef = LoadSimdHelperArgument(instr, 1);
m_lowerer->InsertMove(srcMemRef, instr->UnlinkSrc1(), instr);
IR::Instr * helperCall = IR::Instr::New(Js::OpCode::CALL, this->m_func);
instr->InsertBefore(helperCall);
this->ChangeToHelperCall(helperCall, helper);
m_lowerer->InsertMove(instr->UnlinkDst(), dstMemRef, instr);
return removeInstr(instr);
}
void LowererMD::EmitShiftByScalarI2(IR::Instr *instr, IR::JnHelperMethod helper)
{
IR::Opnd* src2 = instr->GetSrc2();
IR::Opnd* dst = instr->GetDst();
LoadHelperArgument(instr, src2);
IR::MemRefOpnd* srcMemRef = LoadSimdHelperArgument(instr, 0);
m_lowerer->InsertMove(srcMemRef, instr->GetSrc1(), instr);
IR::MemRefOpnd* dstMemRef = LoadSimdHelperArgument(instr, 1);
IR::Instr * helperCall = IR::Instr::New(Js::OpCode::CALL, this->m_func);
instr->InsertBefore(helperCall);
this->ChangeToHelperCall(helperCall, helper);
m_lowerer->InsertMove(dst, dstMemRef, instr);
}
IR::Instr * LowererMD::SIMD128LowerReplaceLane_2(IR::Instr *instr)
{
SList<IR::Opnd*> *args = Simd128GetExtendedArgs(instr);
IR::Opnd *dst = args->Pop();
IR::Opnd *src1 = args->Pop();
IR::Opnd *src2 = args->Pop();
IR::Opnd *src3 = args->Pop();
int lane = src2->AsIntConstOpnd()->AsInt32();
Assert(dst->IsSimd128() && src1->IsSimd128());
if (instr->m_opcode == Js::OpCode::Simd128_ReplaceLane_D2)
{
AssertMsg(AutoSystemInfo::Data.SSE2Available(), "SSE2 not supported");
Assert(src3->IsFloat64());
m_lowerer->InsertMove(dst, src1, instr);
if (lane)
{
instr->InsertBefore(IR::Instr::New(Js::OpCode::SHUFPD, dst, src3, IR::IntConstOpnd::New(0, TyInt8, m_func, true), m_func));
}
else
{
instr->InsertBefore(IR::Instr::New(Js::OpCode::MOVSD, dst, src3, m_func));
}
return removeInstr(instr);
}
Assert(src3->IsInt64());
if (AutoSystemInfo::Data.SSE4_1Available())
{
m_lowerer->InsertMove(dst, src1, instr);
instr->SetDst(dst);
EmitInsertInt64(src3, lane, instr);
}
else
{
LoadHelperArgument(instr, src2);
LoadInt64HelperArgument(instr, src3);
IR::MemRefOpnd* srcMemRef = LoadSimdHelperArgument(instr, 0);
m_lowerer->InsertMove(srcMemRef, src1, instr);
IR::MemRefOpnd* dstMemRef = LoadSimdHelperArgument(instr, 1);
IR::Instr * helperCall = IR::Instr::New(Js::OpCode::CALL, this->m_func);
instr->InsertBefore(helperCall);
this->ChangeToHelperCall(helperCall, IR::HelperSimd128ReplaceLaneI2);
m_lowerer->InsertMove(dst, dstMemRef, instr);
}
return removeInstr(instr);
}
void LowererMD::EmitInsertInt64(IR::Opnd* src, uint index, IR::Instr *instr)
{
IR::Opnd* dst = instr->GetDst();
Assert(dst->IsSimd128() && src->IsInt64());
if (AutoSystemInfo::Data.SSE4_1Available())
{
#ifdef _M_IX86
index *= 2;
Int64RegPair srcPair = m_func->FindOrCreateInt64Pair(src);
instr->InsertBefore(IR::Instr::New(Js::OpCode::PINSRD, dst, srcPair.low, IR::IntConstOpnd::New(index, TyInt8, m_func, true), m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PINSRD, dst, srcPair.high, IR::IntConstOpnd::New(index + 1, TyInt8, m_func, true), m_func));
#else
instr->InsertBefore(IR::Instr::New(Js::OpCode::PINSRQ, dst, src, IR::IntConstOpnd::New(index, TyInt8, m_func, true), m_func));
#endif
}
else
{
intptr_t tempSIMD = m_func->GetThreadContextInfo()->GetSimdTempAreaAddr(0);
#ifdef _M_IX86
Int64RegPair src1Pair = m_func->FindOrCreateInt64Pair(src);
IR::Opnd* lower = IR::MemRefOpnd::New(tempSIMD, TyMachPtr, m_func);
m_lowerer->InsertMove(lower, src1Pair.low, instr);
IR::Opnd* higher = IR::MemRefOpnd::New(tempSIMD + 4, TyMachPtr, m_func);
m_lowerer->InsertMove(higher, src1Pair.high, instr);
#else
IR::Opnd* mem = IR::MemRefOpnd::New(tempSIMD, TyMachPtr, m_func);
m_lowerer->InsertMove(mem, src, instr);
#endif
IR::MemRefOpnd* tmp = IR::MemRefOpnd::New(tempSIMD, TyFloat64, m_func);
Js::OpCode opcode = (index) ? Js::OpCode::MOVHPD : Js::OpCode::MOVLPD;
IR::Instr* newInstr = IR::Instr::New(opcode, dst, tmp, m_func);
instr->InsertBefore(newInstr);
newInstr->HoistMemRefAddress(tmp, Js::OpCode::MOV);
Legalize(newInstr);
}
}
void LowererMD::EmitExtractInt64(IR::Opnd* dst, IR::Opnd* src, uint index, IR::Instr *instr)
{
Assert(index == 0 || index == 1);
Assert(dst->IsInt64() && src->IsSimd128());
if (AutoSystemInfo::Data.SSE4_1Available())
{
#ifdef _M_IX86
index *= 2;
Int64RegPair dstPair = m_func->FindOrCreateInt64Pair(dst);
instr->InsertBefore(IR::Instr::New(Js::OpCode::PEXTRD, dstPair.low, src, IR::IntConstOpnd::New(index, TyInt8, m_func, true), m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PEXTRD, dstPair.high, src, IR::IntConstOpnd::New(index + 1, TyInt8, m_func, true), m_func));
#else
instr->InsertBefore(IR::Instr::New(Js::OpCode::PEXTRQ, dst, src, IR::IntConstOpnd::New(index, TyInt8, m_func, true), m_func));
#endif
}
else
{
IR::Opnd* tmp = src;
if (index)
{
tmp = IR::RegOpnd::New(TySimd128F4, m_func);
instr->InsertBefore(IR::Instr::New(Js::OpCode::PSHUFD, tmp, src, IR::IntConstOpnd::New(2 | 3 << 2, TyInt8, m_func, true), m_func));
}
//kludg-ish; we need a new instruction for LowerReinterpretPrimitive to transform
//and dummy one for a caller to remove
IR::Instr* tmpInstr = IR::Instr::New(Js::OpCode::Simd128_ExtractLane_I2, dst, tmp->UseWithNewType(TyFloat64, m_func), m_func);
instr->InsertBefore(tmpInstr);
m_lowerer->LowerReinterpretPrimitive(tmpInstr);
}
}
IR::Instr* LowererMD::Simd128LowerLdLane(IR::Instr *instr)
{
IR::Opnd* dst, *src1, *src2;
Js::OpCode movOpcode = Js::OpCode::MOVSS;
uint laneWidth = 0, laneIndex = 0, shamt = 0, mask = 0;
IRType laneType = TyInt32;
dst = instr->GetDst();
src1 = instr->GetSrc1();
src2 = instr->GetSrc2();
Assert(dst && dst->IsRegOpnd() && (dst->GetType() == TyFloat32 || dst->GetType() == TyInt32 || dst->GetType() == TyUint32 || dst->GetType() == TyFloat64 || dst->IsInt64()));
Assert(src1 && src1->IsRegOpnd() && src1->IsSimd128());
Assert(src2 && src2->IsIntConstOpnd());
laneIndex = (uint)src2->AsIntConstOpnd()->AsUint32();
laneWidth = 4;
switch (instr->m_opcode)
{
case Js::OpCode::Simd128_ExtractLane_I2:
laneWidth = 8;
break;
case Js::OpCode::Simd128_ExtractLane_F4:
movOpcode = Js::OpCode::MOVSS;
Assert(laneIndex < 4);
break;
case Js::OpCode::Simd128_ExtractLane_I8:
case Js::OpCode::Simd128_ExtractLane_U8:
case Js::OpCode::Simd128_ExtractLane_B8:
movOpcode = Js::OpCode::MOVD;
Assert(laneIndex < 8);
shamt = (laneIndex % 2) * 16;
laneIndex = laneIndex / 2;
laneType = TyInt16;
mask = 0x0000ffff;
break;
case Js::OpCode::Simd128_ExtractLane_I16:
case Js::OpCode::Simd128_ExtractLane_U16:
case Js::OpCode::Simd128_ExtractLane_B16:
movOpcode = Js::OpCode::MOVD;
Assert(laneIndex < 16);
shamt = (laneIndex % 4) * 8;
laneIndex = laneIndex / 4;
laneType = TyInt8;
mask = 0x000000ff;
break;
case Js::OpCode::Simd128_ExtractLane_U4:
case Js::OpCode::Simd128_ExtractLane_I4:
case Js::OpCode::Simd128_ExtractLane_B4:
movOpcode = Js::OpCode::MOVD;
Assert(laneIndex < 4);
break;
default:
Assert(UNREACHED);
}
if (laneWidth == 8) //Simd128_ExtractLane_I2
{
EmitExtractInt64(dst, instr->GetSrc1(), laneIndex, instr);
}
else
{
IR::Opnd* tmp = src1;
if (laneIndex != 0)
{
// tmp = PSRLDQ src1, shamt
tmp = IR::RegOpnd::New(src1->GetType(), m_func);
IR::Instr *shiftInstr = IR::Instr::New(Js::OpCode::PSRLDQ, tmp, src1, IR::IntConstOpnd::New(laneWidth * laneIndex, TyInt8, m_func, true), m_func);
instr->InsertBefore(shiftInstr);
Legalize(shiftInstr);
}
// MOVSS/MOVSD/MOVD dst, tmp
instr->InsertBefore(IR::Instr::New(movOpcode, movOpcode == Js::OpCode::MOVD ? dst : dst->UseWithNewType(tmp->GetType(), m_func), tmp, m_func));
}
// dst has the 4-byte lane
if (instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I8 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_U8 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B8 ||
instr->m_opcode == Js::OpCode::Simd128_ExtractLane_U16 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I16 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B16)
{
// extract the 1/2 bytes sublane
IR::Instr *newInstr = nullptr;
if (shamt != 0)
{
// SHR dst, dst, shamt
newInstr = IR::Instr::New(Js::OpCode::SHR, dst, dst, IR::IntConstOpnd::New((IntConstType)shamt, TyInt8, m_func), m_func);
instr->InsertBefore(newInstr);
Legalize(newInstr);
}
Assert(laneType == TyInt8 || laneType == TyInt16);
// zero or sign-extend upper bits
if (instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I8 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I16)
{
if (laneType == TyInt8)
{
IR::RegOpnd * tmp = IR::RegOpnd::New(TyInt8, m_func);
newInstr = IR::Instr::New(Js::OpCode::MOV, tmp, dst, m_func);
instr->InsertBefore(newInstr);
Legalize(newInstr);
newInstr = IR::Instr::New(Js::OpCode::MOVSX, dst, tmp, m_func);
}
else
{
newInstr = IR::Instr::New(Js::OpCode::MOVSXW, dst, dst->UseWithNewType(laneType, m_func), m_func);
}
}
else
{
newInstr = IR::Instr::New(Js::OpCode::AND, dst, dst, IR::IntConstOpnd::New(mask, TyInt32, m_func), m_func);
}
instr->InsertBefore(newInstr);
Legalize(newInstr);
}
if (instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B4 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B8 ||
instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B16)
{
IR::Instr* pInstr = nullptr;
IR::RegOpnd* tmp = IR::RegOpnd::New(TyInt8, m_func);
// cmp dst, 0
pInstr = IR::Instr::New(Js::OpCode::CMP, m_func);
pInstr->SetSrc1(dst->UseWithNewType(laneType, m_func));
pInstr->SetSrc2(IR::IntConstOpnd::New(0, laneType, m_func, true));
instr->InsertBefore(pInstr);
Legalize(pInstr);
// mov tmp(TyInt8), dst
pInstr = IR::Instr::New(Js::OpCode::MOV, tmp, dst, m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
// setne tmp(TyInt8)
pInstr = IR::Instr::New(Js::OpCode::SETNE, tmp, tmp, m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
// movsx dst, tmp(TyInt8)
instr->InsertBefore(IR::Instr::New(Js::OpCode::MOVSX, dst, tmp, m_func));
}
IR::Instr* prevInstr = instr->m_prev;
instr->Remove();
return prevInstr;
}
IR::Instr* LowererMD::Simd128LowerSplat(IR::Instr *instr)
{
Js::OpCode shufOpCode = Js::OpCode::SHUFPS, movOpCode = Js::OpCode::MOVSS;
IR::Opnd *dst, *src1;
IR::Instr *pInstr = nullptr;
dst = instr->GetDst();
src1 = instr->GetSrc1();
Assert(dst && dst->IsRegOpnd() && dst->IsSimd128());
Assert(src1 && src1->IsRegOpnd() && (src1->GetType() == TyFloat32 || src1->GetType() == TyInt32 || src1->GetType() == TyFloat64 ||
src1->GetType() == TyInt16 || src1->GetType() == TyInt8 || src1->GetType() == TyUint16 ||
src1->GetType() == TyUint8 || src1->GetType() == TyUint32 || src1->IsInt64()));
Assert(!instr->GetSrc2());
IR::Opnd* tempTruncate = nullptr;
bool bSkip = false;
IR::LabelInstr *labelZero = IR::LabelInstr::New(Js::OpCode::Label, m_func);
IR::LabelInstr *labelDone = IR::LabelInstr::New(Js::OpCode::Label, m_func);
switch (instr->m_opcode)
{
case Js::OpCode::Simd128_Splat_F4:
shufOpCode = Js::OpCode::SHUFPS;
movOpCode = Js::OpCode::MOVSS;
break;
case Js::OpCode::Simd128_Splat_I4:
case Js::OpCode::Simd128_Splat_U4:
shufOpCode = Js::OpCode::PSHUFD;
movOpCode = Js::OpCode::MOVD;
break;
case Js::OpCode::Simd128_Splat_D2:
shufOpCode = Js::OpCode::SHUFPD;
movOpCode = Js::OpCode::MOVSD;
break;
case Js::OpCode::Simd128_Splat_I2:
{
EmitInsertInt64(src1, 0, instr);
instr->InsertBefore(IR::Instr::New(Js::OpCode::PSHUFD, dst, dst, IR::IntConstOpnd::New(68, TyInt8, m_func, true), m_func));
bSkip = true;
break;
}
case Js::OpCode::Simd128_Splat_I8:
case Js::OpCode::Simd128_Splat_U8:
// MOV tempTruncate(bx), src1: truncate the value to 16bit int
// MOVD dst, tempTruncate(bx)
// PUNPCKLWD dst, dst
// PSHUFD dst, dst, 0
tempTruncate = EnregisterIntConst(instr, src1, TyInt16);
instr->InsertBefore(IR::Instr::New(Js::OpCode::MOVD, dst, tempTruncate, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PUNPCKLWD, dst, dst, dst, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PSHUFD, dst, dst, IR::IntConstOpnd::New(0, TyInt8, m_func, true), m_func));
bSkip = true;
break;
case Js::OpCode::Simd128_Splat_I16:
case Js::OpCode::Simd128_Splat_U16:
// MOV tempTruncate(bx), src1: truncate the value to 8bit int
// MOVD dst, tempTruncate(bx)
// PUNPCKLBW dst, dst
// PUNPCKLWD dst, dst
// PSHUFD dst, dst, 0
tempTruncate = EnregisterIntConst(instr, src1, TyInt8);
instr->InsertBefore(IR::Instr::New(Js::OpCode::MOVD, dst, tempTruncate, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PUNPCKLBW, dst, dst, dst, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PUNPCKLWD, dst, dst, dst, m_func));
instr->InsertBefore(IR::Instr::New(Js::OpCode::PSHUFD, dst, dst, IR::IntConstOpnd::New(0, TyInt8, m_func, true), m_func));
bSkip = true;
break;
case Js::OpCode::Simd128_Splat_B4:
case Js::OpCode::Simd128_Splat_B8:
case Js::OpCode::Simd128_Splat_B16:
// CMP src1, 0
// JEQ $labelZero
// MOVAPS dst, xmmword ptr[X86_ALL_NEG_ONES]
// JMP $labelDone
// $labelZero:
// XORPS dst, dst
// $labelDone:
//pInstr = IR::Instr::New(Js::OpCode::CMP, src1, IR::IntConstOpnd::New(0, TyInt8, m_func, true), m_func);
//instr->InsertBefore(pInstr);
//Legalize(pInstr);
// cmp src1, 0000h
pInstr = IR::Instr::New(Js::OpCode::CMP, m_func);
pInstr->SetSrc1(src1);
pInstr->SetSrc2(IR::IntConstOpnd::New(0x0000, TyInt32, m_func, true));
instr->InsertBefore(pInstr);
Legalize(pInstr);
//JEQ $labelZero
instr->InsertBefore(IR::BranchInstr::New(Js::OpCode::JEQ, labelZero, m_func));
// MOVAPS dst, xmmword ptr[X86_ALL_NEG_ONES]
pInstr = IR::Instr::New(Js::OpCode::MOVAPS, dst, IR::MemRefOpnd::New(m_func->GetThreadContextInfo()->GetX86AllNegOnesAddr(), TySimd128I4, m_func), m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
// JMP $labelDone
instr->InsertBefore(IR::BranchInstr::New(Js::OpCode::JMP, labelDone, m_func));
// $labelZero:
instr->InsertBefore(labelZero);
// XORPS dst, dst
instr->InsertBefore(IR::Instr::New(Js::OpCode::XORPS, dst, dst, dst, m_func)); // make dst to be 0
// $labelDone:
instr->InsertBefore(labelDone);
bSkip = true;
break;
default:
Assert(UNREACHED);
}
if (instr->m_opcode == Js::OpCode::Simd128_Splat_F4 && instr->GetSrc1()->IsFloat64())
{
IR::RegOpnd *regOpnd32 = IR::RegOpnd::New(TyFloat32, this->m_func);
// CVTSD2SS regOpnd32.f32, src.f64 -- Convert regOpnd from f64 to f32
instr->InsertBefore(IR::Instr::New(Js::OpCode::CVTSD2SS, regOpnd32, src1, this->m_func));
src1 = regOpnd32;
}
if (!bSkip)
{
instr->InsertBefore(IR::Instr::New(movOpCode, dst, src1, m_func));
instr->InsertBefore(IR::Instr::New(shufOpCode, dst, dst, IR::IntConstOpnd::New(0, TyInt8, m_func, true), m_func));
}
IR::Instr* prevInstr = instr->m_prev;
instr->Remove();
return prevInstr;
}
IR::Instr* LowererMD::Simd128LowerSqrt(IR::Instr *instr)
{
Js::OpCode opcode = Js::OpCode::SQRTPS;
IR::Opnd *dst, *src1;
dst = instr->GetDst();
src1 = instr->GetSrc1();
Assert(dst && dst->IsRegOpnd());
Assert(src1 && src1->IsRegOpnd());
Assert(instr->GetSrc2() == nullptr);
opcode = Js::OpCode::SQRTPS;
#if 0
{
Assert(instr->m_opcode == Js::OpCode::Simd128_Sqrt_D2);
opcode = Js::OpCode::SQRTPD;
}
#endif // 0
instr->InsertBefore(IR::Instr::New(opcode, dst, src1, m_func));
IR::Instr* prevInstr = instr->m_prev;
instr->Remove();
return prevInstr;
}
IR::Instr* LowererMD::Simd128LowerNeg(IR::Instr *instr)
{
IR::Opnd* dst = instr->GetDst();
IR::Opnd* src1 = instr->GetSrc1();
Js::OpCode addOpcode = Js::OpCode::PADDD;
ThreadContextInfo* threadContextInfo = m_func->GetThreadContextInfo();
intptr_t allOnes = threadContextInfo->GetX86AllOnesI4Addr();
Assert(dst->IsRegOpnd() && dst->IsSimd128());
Assert(src1->IsRegOpnd() && src1->IsSimd128());
Assert(instr->GetSrc2() == nullptr);
switch (instr->m_opcode)
{
case Js::OpCode::Simd128_Neg_I4:
case Js::OpCode::Simd128_Neg_U4:
break;
case Js::OpCode::Simd128_Neg_I8:
case Js::OpCode::Simd128_Neg_U8:
addOpcode = Js::OpCode::PADDW;
allOnes = threadContextInfo->GetX86AllOnesI8Addr();
break;
case Js::OpCode::Simd128_Neg_I16:
case Js::OpCode::Simd128_Neg_U16:
addOpcode = Js::OpCode::PADDB;
allOnes = threadContextInfo->GetX86AllOnesI16Addr();
break;
default:
Assert(UNREACHED);
}
// MOVAPS dst, src1
IR::Instr *pInstr = IR::Instr::New(Js::OpCode::MOVAPS, dst, src1, m_func);
instr->InsertBefore(pInstr);
// PANDN dst, dst, 0xfff...f
pInstr = IR::Instr::New(Js::OpCode::PANDN, dst, dst, IR::MemRefOpnd::New(threadContextInfo->GetX86AllNegOnesAddr(), src1->GetType(), m_func), m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
// addOpCode dst, dst, {allOnes}
pInstr = IR::Instr::New(addOpcode, dst, dst, IR::MemRefOpnd::New(allOnes, src1->GetType(), m_func), m_func);
instr->InsertBefore(pInstr);
Legalize(pInstr);
pInstr = instr->m_prev;
instr->Remove();
return pInstr;
}
IR::Instr* LowererMD::Simd128LowerMulI4(IR::Instr *instr)
{
Assert(instr->m_opcode == Js::OpCode::Simd128_Mul_I4 || instr->m_opcode == Js::OpCode::Simd128_Mul_U4);
IR::Instr *pInstr;
IR::Opnd* dst = instr->GetDst();
IR::Opnd* src1 = instr->GetSrc1();
IR::Opnd* src2 = instr->GetSrc2();
IR::Opnd* temp1, *temp2, *temp3;
Assert(dst->IsRegOpnd() && dst->IsSimd128());
Assert(src1->IsRegOpnd() && src1->IsSimd128());
Assert(src2->IsRegOpnd() && src2->IsSimd128());
temp1 = IR::RegOpnd::New(src1->GetType(), m_func);
temp2 = IR::RegOpnd::New(src1->GetType(), m_func);
temp3 = IR::RegOpnd::New(src1->GetType(), m_func);
// temp1 = PMULUDQ src1, src2
pInstr = IR::Instr::New(Js::OpCode::PMULUDQ, temp1, src1, src2, m_func);
instr->InsertBefore(pInstr);
//MakeDstEquSrc1(pInstr);
Legalize(pInstr);