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@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.3k 631

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.5k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.6k 242

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 348

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 883 230

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 745 181

Repositories

Showing 10 of 110 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 15 Apache-2.0 10 23 2 Updated Jun 20, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 96 Apache-2.0 55 89 16 Updated Jun 20, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 119 Apache-2.0 62 142 55 Updated Jun 20, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 328 ISC 82 47 (5 issues need help) 16 Updated Jun 19, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 22 Apache-2.0 20 43 8 Updated Jun 19, 2025
  • t1 Public

    The highest performace Cray-like RISC-V Vector in the world.

    chipsalliance/t1’s past year of commit activity
    Scala 272 Apache-2.0 38 18 24 Updated Jun 19, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 28 Apache-2.0 6 20 4 Updated Jun 19, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    302 Apache-2.0 44 44 9 Updated Jun 19, 2025
  • chips-alliance-website Public
    chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 4 MIT 6 8 8 Updated Jun 19, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,303 Apache-2.0 631 335 (1 issue needs help) 148 Updated Jun 18, 2025
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