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Jpnock/mips-verilog-cpu
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- Add build instructions - Add test instructions - Add dependencies
  • Jpnock
  • Opened 
    on Dec 12, 2021
  • #61

Jpnock/mips-verilog-cpu
Edge case testing

After reading the spec, I found a number of cases where our CPU was not complying with edge-cases of the MIPS I ISA. We should write tests for these and include them in our test bench I ve categorised ...
enhancement
help wanted
  • Jpnock
  • 1
  • Opened 
    on Dec 4, 2021
  • #47

Jpnock/mips-verilog-cpu
Read operation byte-enables

I need to double check that these follow the same logic as the byte-enables for writes. We can easily do this by enforcing that bytes without a read-enable get filled with rubbish data. If the tests still ...
bug
question
  • Jpnock
  • 1
  • Opened 
    on Dec 3, 2021
  • #41

Jpnock/mips-verilog-cpu
Avalon testing

It d be good to have a testbench, for both ourselves and as part of the submission, which tests waitrequest on the Avalon interface. This could be done as part of the load/store instruction testing.
  • Jpnock
  • Opened 
    on Nov 30, 2021
  • #37

Jpnock/mips-verilog-cpu
Load/Store instructions (non-word alignment)

The non-word versions of these instructions need to be fixed as they currently only work for addresses that are word-aligned. If a non-word aligned address is used, the stored/loaded byte would be incorrect. ...
bug
  • Jpnock
  • Opened 
    on Nov 29, 2021
  • #35

Jpnock/mips-verilog-cpu
Test benches

- Only test one instruction per test case - The first line of the test case must be the value to expect in register v0 - This must be of the form # Expect: 0x41424344 - The last line of the ...
help wanted
  • Jpnock
  • 1
  • Opened 
    on Nov 26, 2021
  • #27

Jpnock/mips-verilog-cpu
Halting

The CPU is considered to halt when it executes the instruction at address 0 This needs to be implemented and checked to make sure the implemented logic works on reset.
  • Jpnock
  • Opened 
    on Nov 23, 2021
  • #24

Jpnock/mips-verilog-cpu
Updating PC on FETCH

Wondering if we could simplify some of the delay slot logic by updating the PC during FETCH rather than EXEC2. The flow would be something like this: 1) FETCH : PC updated to PC + 4. 2) EXEC1 : Jump ...
  • dharmilshah99
  • 8
  • Opened 
    on Nov 23, 2021
  • #22

Jpnock/mips-verilog-cpu
Byte enable information

Reposted from David Thomas in the Teams Question chat If you only wanted byte 2 to be written, then yes the byteenable would be 0b0100. However, in the example the write is of 2 bytes starting at address ...
documentation
  • Jpnock
  • 2
  • Opened 
    on Nov 22, 2021
  • #19

Jpnock/mips-verilog-cpu
Reset behaviour

We should standardise reset behaviour across the different units. For example, register file will reset as long as reset is high during the posedge of the clock whereas PC only resets if reset was high ...
question
  • Jpnock
  • 3
  • Opened 
    on Nov 22, 2021
  • #17
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