Skip to content

Pull requests: llvm/circt

New pull request New
159 Open 6,135 Closed
159 Open 6,135 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[Support] Factor out unused op pruning from LLHD Mem2Reg; NFC
#8531 opened Jun 3, 2025 by fabianschuiki Loading…
3
[AIG] Add LongestPathAnalysis implementation
#8529 opened Jun 3, 2025 by uenoku Loading…
[CMake] Allow Python discovery from virtual environment
#8520 opened May 30, 2025 by hamidelmaazouz Loading…
5
[SV] Enhanced name validation: support IEEE standard escape name checking
#8518 opened May 29, 2025 by RonxBulld Loading…
8
[CI] Bump docker images
#8500 opened May 21, 2025 by hovind Loading…
1
[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480 opened May 13, 2025 by jiahanxie353 Loading…
3
[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446 opened Apr 25, 2025 by jiahanxie353 Loading…
[ci] Bump CI images
#8445 opened Apr 25, 2025 by seldridge Loading…
2
[PyRTG] Refactor targets/configs RTG Involving the `rtg` dialect
#8399 opened Apr 7, 2025 by maerhart Loading…
[RTG] Add MemoryAllocation pass to pipeline RTG Involving the `rtg` dialect
#8397 opened Apr 6, 2025 by maerhart Loading…
[RTG] Add MemoryAllocation pass RTG Involving the `rtg` dialect
#8395 opened Apr 6, 2025 by maerhart Loading…
1
[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392 opened Apr 4, 2025 by AnnuCode Loading…
2
[RTG][Elaboration] Improve how tests are matched with targets RTG Involving the `rtg` dialect
#8391 opened Apr 4, 2025 by maerhart Loading…
[RTG][Elaboration] Treat randomized sequences as regular identity values RTG Involving the `rtg` dialect
#8389 opened Apr 3, 2025 by maerhart Loading…
[RTG][Elaboration] Properly handle values with identity RTG Involving the `rtg` dialect
#8388 opened Apr 3, 2025 by maerhart Loading…
When replacing a register with its reset value, attempt width coercion FIRRTL Involving the `firrtl` dialect
#8379 opened Apr 1, 2025 by rwy7 Loading…
[ImportVerilog]add support for String literal operations
#8309 opened Mar 10, 2025 by ChenXo0 • Draft
2
Add a few mux-of-const and reg-of-and/or canonicalizers. FIRRTL Involving the `firrtl` dialect
#8307 opened Mar 7, 2025 by rwy7 Loading…
17
[circt-verilog-lsp] Add hover support
#8304 opened Mar 6, 2025 by uenoku Loading…
3
[circt-verilog-lsp] Add inlay hints support for Verilog LSP server
#8303 opened Mar 6, 2025 by uenoku Loading…
3
[Firtool] Move from lib to lib/Tools, NFC
#8291 opened Mar 3, 2025 by uenoku Loading…
[circt-verilog-lsp][vscode] Add initial VS Code extension configuration for CIRCT Verilog LSP
#8281 opened Feb 27, 2025 by uenoku Loading…
1
[circt-verilog-lsp] Add definition and reference providers
#8280 opened Feb 27, 2025 by uenoku Loading…
4
[ImportVerilog] add unpacked array concatenation Moore
#8270 opened Feb 24, 2025 by chenbo-again Loading…
1
10
[circt-synth] Implemented AIG node balancing algorithm
#8262 opened Feb 21, 2025 by Max-astro Loading…
28
ProTip! Filter pull requests by the default branch with base:main.