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[Feature request] adding FHDL module to synthesizable VHDL support

Status: Open.

#311 In m-labs/migen;

· ohault opened on May 30, 2025

Invalid verilog representation

Status: Open.

#308 In m-labs/migen;

· ollie-etl opened on May 6, 2025

VCD file may contain time stamps as floats

Status: Open.

#306 In m-labs/migen;

· oscargus opened on Apr 16, 2025

<code>fsm.delayed_enter</code> incompatible with vcd dump

Status: Open.

#305 In m-labs/migen;

· enurseitov opened on Apr 15, 2025

Support for negedge sensitivity list

Status: Open.

#304 In m-labs/migen;

· shantzis62 opened on Apr 12, 2025

assignment of combinatorial values with delayed assignment gives incorrect results when referencing same signal

Status: Open.

#303 In m-labs/migen;

· jwise opened on Mar 11, 2025

Support for python 3.13

Status: Open.

#297 In m-labs/migen;

· jasonbridges opened on Dec 2, 2024

Async FIFO Output is Broken when FIFO Depth is Set to 2

Status: Open.

#296 In m-labs/migen;

· linuswck opened on Nov 15, 2024

<code>else</code> branch elided in generated Verilog

Status: Open.

#274 In m-labs/migen;

· McSherry opened on Jun 22, 2023

Better FMC support

Status: Open.

#269 In m-labs/migen;

· kaolpr opened on Nov 25, 2022

[Sim] Error with fsm delayed_enter method

Status: Open.

#267 In m-labs/migen;

· kamejoko80 opened on Oct 7, 2022

move the conditional part of <code>toolchain.build(run=True/False)</code> to a separate method

Status: Open.

#258 In m-labs/migen;

· lneuhaus opened on Feb 22, 2022