[ExportVerilog] Allow escaped names for ports and variables etc

[uenoku]

  hw.module @aiger_top(in %a5B05D "\\a[0]" : i1, in %a5B15D "\\a[1]" : i1, in %b5B05D "\\b[0]" : i1, in %b5B15D "\\b[1]" : i1, out "\\c[0]" : i1, out "\\c[1]" : i1) {
    %true = hw.constant true
    %0 = comb.xor bin %b5B15D, %true : i1
    %1 = comb.xor bin %a5B15D, %true : i1
    %2 = comb.and bin %0, %1 : i1
    %true_0 = hw.constant true
    %3 = comb.xor bin %b5B05D, %true_0 : i1
    %4 = comb.xor bin %a5B05D, %true_0 : i1
    %5 = comb.and bin %3, %4 : i1
    hw.output %2, %5 : i1, i1
  } 

$circt-opt -export-verilog %s

module aiger_top(       // bar.mlir:1:3
  input  _5Ca5B05D,     // bar.mlir:1:27
         _5Ca5B15D,     // bar.mlir:1:53
         _5Cb5B05D,     // bar.mlir:1:79
         _5Cb5B15D,     // bar.mlir:1:105
  output _5Cc5B05D,     // bar.mlir:1:132
         _5Cc5B15D      // bar.mlir:1:151
);

  wire _GEN = ~_5Cb5B15D & ~_5Ca5B15D;  // bar.mlir:3:10, :4:10, :5:10
  assign _5Cc5B05D = _GEN;      // bar.mlir:5:10, :10:5
  assign _5Cc5B15D = _GEN;      // bar.mlir:5:10, :10:5
endmodule

It's nice if we don't have to legalize \a[0]. eef60c8 handles instance/module names but not for signals.

[fabianschuiki]

This would be really useful!