[ImportVerilog] Unknown module instantiation fails even with `--ignore-unknown-modules`

[uenoku]

module test(    // bar.mlir:2:1
  input  [1:0] a,       // bar.mlir:2:20
  input  [2:0] b,       // bar.mlir:2:31
  output [3:0] c,       // bar.mlir:2:43
  output [4:0] d        // bar.mlir:2:54
);

  ext e (       // bar.mlir:3:12
    .a (a),
    .b (b),
    .c (c),
    .d (d)
  );    // bar.mlir:3:12
endmodule

$ circt-verilog %s --ignore-unknown-modules
foo.sv:9:7: error: unsupported module member: UninstantiatedDef
  ext e (       // bar.mlir:3:12
      ^