verilog-hdl
Here are 655 public repositories matching this topic...
VUnit is a unit testing framework for VHDL/SystemVerilog
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May 11, 2025 - VHDL
Python-based Hardware Design Processing Toolkit for Verilog HDL
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Jun 15, 2024 - Python
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Apr 30, 2024 - Verilog
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
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Oct 17, 2023 - Python
HDL support for VS Code
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Jul 11, 2025 - TypeScript
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
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Aug 10, 2024 - Python
High throughput JPEG decoder in Verilog for FPGA
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Mar 5, 2022 - Verilog
Image Processing Toolbox in Verilog using Basys3 FPGA
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May 20, 2025 - VHDL
A complete open-source design-for-testing (DFT) Solution
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May 28, 2025 - Swift
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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Jun 20, 2024 - Verilog
A simple implementation of a UART modem in Verilog.
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Nov 10, 2021 - Verilog
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
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Jan 29, 2024 - Verilog
5-stage pipelined 32-bit MIPS microprocessor in Verilog
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Apr 3, 2020 - Verilog
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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Dec 29, 2024 - Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
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Jul 31, 2022 - Verilog
中山大学计算机组成原理实验 (2018 秋):用 Verilog 设计并实现的简易单周期和多周期 CPU
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Mar 21, 2021 - Verilog
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
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May 26, 2019 - Verilog
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
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Dec 5, 2019 - C
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
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