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Greyhound on IHP SG13G2 0.13 μm BiCMOS process

Verilog 19 Updated Apr 14, 2025

IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]

Verilog 4 17 Updated Apr 11, 2025

Pi Pico/RP2040 Simulator with advanced functionality.

Shell 2 Updated Mar 26, 2025

Microphotography viewer based on Leaflet.js

JavaScript 43 5 Updated Dec 15, 2023

HPDL 1414 Pmod Module

Verilog 2 Updated Mar 6, 2025

Firmware for FarmHub devices

C++ 2 Updated Apr 15, 2025

Structural Netlist API (and more) for EDA post synthesis flow development

Verilog 93 14 Updated Apr 11, 2025

CH32V003-based 2xSNES controller interface PMOD

C++ 5 Updated Mar 26, 2025

Atari 2600 Open-source System-on-Chip (SoC)

Python 32 2 Updated Mar 20, 2025

A backup decryptor and OTP generator for the vault of the Aegis Authenticator Android app.

Python 16 2 Updated Feb 11, 2025

SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

Python 10 Updated Sep 2, 2024

An JLC PCB Fabrication Plugin for KiCad

Python 434 68 Updated Mar 25, 2025

Convert any LCSC components (including EasyEDA) to KiCad library

Python 881 92 Updated Feb 11, 2025

Example SDL3 application for ESP32

C 12 Updated Apr 14, 2025

AudioSample is an optimized numpy-like audio manipulation library, created for researchers, used by developers.

Jupyter Notebook 87 3 Updated Mar 30, 2025

HV prototyping for sky130 sonos program/erase

1 Updated Jul 16, 2024

Recipe: Persistent Network Configuration in WSL 2 using Hyper-V Virtual Switch

49 7 Updated Mar 20, 2024

Submission template for Tiny Tapeout 7 - Chisel HDL Projects

Tcl 3 1 Updated Jul 26, 2024

Waveform Viewer Extension for VScode

TypeScript 135 5 Updated Apr 16, 2025

Curriculum for a university course to teach chip design using open source EDA tools

Jupyter Notebook 64 13 Updated Oct 21, 2023

RISC-V RV32E core designed for minimal area

Verilog 14 1 Updated Nov 17, 2024

Peggy: Parser generator for JavaScript

JavaScript 1,042 67 Updated Apr 15, 2025

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

C 373 24 Updated Apr 16, 2025

Running FreeRTOS on an STM32 Nucleo-C031C6 with Wokwi Simulation in VSCode.

C 12 3 Updated Feb 23, 2024

The next generation of OpenLane, rewritten from scratch with a modular architecture

Python 280 59 Updated Feb 26, 2025

Transform URLs in strings to actual links.

TypeScript 9 Updated Feb 17, 2022

Spike, a RISC-V ISA Simulator

C 2,652 921 Updated Apr 15, 2025

Performance-optimized container images for building Zephyr RTOS applications.

Dockerfile 51 1 Updated Oct 22, 2024

Charliplexing is a scheme for multiplexing access to components, like LEDs, switches, touch sensors etc.

JavaScript 4 Updated Jan 7, 2024
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