Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.4k 632

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.5k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.6k 244

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 350

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 884 231

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 747 181

Repositories

Showing 10 of 110 repositories
  • t1 Public
    Scala 279 Apache-2.0 38 18 26 Updated Jul 24, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    313 Apache-2.0 49 52 5 Updated Jul 24, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    Rust 17 Apache-2.0 13 27 5 Updated Jul 24, 2025
  • i3c-core Public
    SystemVerilog 31 Apache-2.0 10 4 1 Updated Jul 24, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    Rust 120 Apache-2.0 63 146 67 Updated Jul 24, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    HTML 7 6 0 0 Updated Jul 24, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    SystemVerilog 24 Apache-2.0 21 41 7 Updated Jul 24, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    SystemVerilog 333 ISC 83 46 (5 issues need help) 20 Updated Jul 24, 2025
  • caliptra-dpe Public

    High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

    Rust 17 Apache-2.0 26 16 11 Updated Jul 23, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ 39 LGPL-3.0 693 0 0 Updated Jul 23, 2025