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  • UART Public

    This project implements a UART (Universal Asynchronous Receiver-Transmitter) in Verilog

    uart
    Verilog Updated Oct 5, 2024

  • MIPS-Multi-Cycle-32-bit Public

    This project implements a 32-bit multicycle MIPS processor in Verilog. The design is based on a multicycle architecture that executes instructions in multiple stages, reducing the complexity of the…

    mips computer-architecture multicycle-processor
    Verilog Updated Oct 5, 2024

  • MIPS-Single-Cycle-32-bit Public

    this project implements a 32-bit single-cycle MIPS processor in Verilog. The design supports a subset of MIPS instructions and is aimed at simulating basic arithmetic, logical, and control flow ope…

    mips computer-architecture
    Verilog Updated Oct 5, 2024

  • FIFO Public

    fifo
    Verilog Updated Sep 21, 2024

  • Digital-Logic-Circuits-Basics Public

    This repository serves as a resource for digital circuits main components. The circuits are described using Verilog hardware description language (HDL). The repository includes a range of combinati…

    Verilog Updated Sep 21, 2024

  • String.H Public

    STRING.H

    C Updated Aug 13, 2023