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@Purdue-SoCET

Purdue System on Chip Extension Technologies

A student team working on designing and testing an SoC at Purdue University

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  1. RISCVBusiness RISCVBusiness Public

    Forked from JakeStevens/RISCVBusiness

    SystemVerilog 8 3

  2. vortex vortex Public

    Forked from vortexgpgpu/vortex

    Verilog 4 1

  3. AFTx06_Caravel AFTx06_Caravel Public

    Verilog 3 2

  4. AFTx05_Public AFTx05_Public Public

    Verilog 2 1

  5. SAFE SAFE Public

    Python 2 2

  6. FPU FPU Public

    Floating-point unit for RISC-V core

    SystemVerilog 2 1

Repositories

Showing 10 of 50 repositories
  • intro-2-stopwatch Public
    C++ 1 0 0 0 Updated Mar 10, 2025
  • chiplet-components Public
    SystemVerilog 1 0 0 0 Updated Mar 10, 2025
  • gpgpu-sim_distribution Public Forked from gpgpu-sim/gpgpu-sim_distribution

    GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

    C++ 0 543 0 0 Updated Mar 10, 2025
  • RISCVBusiness Public Forked from JakeStevens/RISCVBusiness
    SystemVerilog 8 8 1 (1 issue needs help) 5 Updated Mar 10, 2025
  • tensor-core Public
    SystemVerilog 2 0 0 1 Updated Mar 9, 2025
  • vito-uart Public
    SystemVerilog 0 Apache-2.0 2 1 0 Updated Mar 7, 2025
  • riscv_intro Public
    SystemVerilog 0 0 0 0 Updated Mar 6, 2025
  • AXI-UVM Public
    SystemVerilog 0 0 0 0 Updated Mar 2, 2025
  • vortexS25 Public Forked from vortexgpgpu/vortex
    Verilog 0 Apache-2.0 299 0 0 Updated Feb 26, 2025
  • vortex-f24 Public Forked from vortexgpgpu/vortex
    Verilog 1 Apache-2.0 299 0 0 Updated Feb 23, 2025
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