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VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

142 followers
Santa Cruz, CA
http://vlsida.github.io
mrg+vlsida@ucsc.edu

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Repositories 30
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OpenRAM Public

An open-source static random access memory (SRAM) compiler.

Python 876 216
openram-docker-image Public

Shell 5 1
openram-vagrant-image Public

Settings to build a Vagrant image for OpenRAM

Shell 3 1

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Showing 10 of 30 repositories

sky130_fd_bd_sram Public

0 Apache-2.0 0 0 0 Updated Mar 10, 2025
openlane2 Public Forked from efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture

Python 0 Apache-2.0 56 0 0 Updated Feb 26, 2025
chip-tutorials Public

Python 1 Apache-2.0 1 0 0 Updated Feb 20, 2025
vlsida-openroad Public

Dockerfile 0 0 0 0 Updated Nov 21, 2024
OpenRAM Public
An open-source static random access memory (SRAM) compiler.

Python 876 BSD-3-Clause 216 42 (2 issues need help) 9 Updated Nov 14, 2024
OpenROAD Public Forked from The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow

Verilog 4 BSD-3-Clause 618 0 0 Updated Oct 10, 2024
openram_testchip Public Forked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io

Verilog 9 Apache-2.0 348 0 1 Updated Aug 7, 2024
sky130_sram_macros Public

SourcePawn 12 Apache-2.0 15 1 0 Updated Jul 12, 2024
OpenCache Public
An open-source custom cache generator.

Python 30 BSD-3-Clause 5 1 0 Updated Mar 14, 2024
vlsida-eda Public
Conda recipes for VLSIDA projects.

Shell 5 BSD-3-Clause 0 0 0 Updated Dec 20, 2023

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