This document describes overlays provided in the kernel packages
For generic Armbian overlays documentation please see
https://docs.armbian.com/Hardware_Allwinner_overlays/

### Platform:

sun50i-a64 (Allwinner A64)

### Platform details:

Supported pin banks: PB, PC, PD, PH

Both SPI controllers have only one hardware CS pin exposed,
adding fixed software (GPIO) chip selects is possible with a separate overlay

I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available
on supported boards, so this controller is not supported in provided overlays

### Provided overlays:

- i2c0
- i2c1
- pps-gpio
- spi-add-cs1
- spi-jedec-nor
- spi-spidev
- uart1
- uart2
- uart3
- uart4
- w1-gpio

### Overlay details:

### i2c0

Activates TWI/I2C bus 0

I2C0 pins (SCL, SDA): PH0, PH1

### i2c1

Activates TWI/I2C bus 1

I2C1 pins (SCL, SDA): PH2, PH3

### pps-gpio

Activates pulse-per-second GPIO client

Parameters:

param_pps_pin (pin)
	Pin PPS source is connected to
	Optional
	Default: PD4

param_pps_falling_edge (bool)
	Assert by falling edge
	Optional
	Default: 0
	When set (to 1), assert is indicated by a falling edge
		(instead of by a rising edge)

### spi-add-cs1

Adds support for using SPI chip select 1 with GPIO for both SPI controllers
Respective GPIO will be claimed only if controller is enabled by another overlay
This overlay is required for using chip select 1 with other SPI overlays

SPI 0 pins (CS1): PB6
SPI 1 pins (CS1): PD6

### spi-jedec-nor

Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
supported by the kernel SPI NOR driver

SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0

Parameters:

param_spinor_spi_bus (int)
	SPI bus to activate SPI NOR flash support on
	Required
	Supported values: 0, 1

param_spinor_spi_cs (int)
	SPI chip select number
	Optional
	Default: 0
	Supported values: 0, 1
	Using chip select 1 requires using "spi-add-cs1" overlay

param_spinor_max_freq (int)
	Maximum SPI frequency
	Optional
	Default: 1000000
	Range: 3000 - 100000000

### spi-spidev

Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
where X is the bus number and Y is the CS number

SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0

Parameters:

param_spidev_spi_bus (int)
	SPI bus to activate SPIdev support on
	Required
	Supported values: 0, 1

param_spidev_spi_cs (int)
	SPI chip select number
	Optional
	Default: 0
	Supported values: 0, 1
	Using chip select 1 requires using "spi-add-cs1" overlay

param_spidev_max_freq (int)
	Maximum SPIdev frequency
	Optional
	Default: 1000000
	Range: 3000 - 100000000

### uart1

Activates serial port 1 (/dev/ttyS1)

UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9

Parameters:

param_uart1_rtscts (bool)
	Enable RTS and CTS pins
	Optional
	Default: 0
	Set to 1 to enable

### uart2

Activates serial port 2 (/dev/ttyS2)

UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3

Parameters:

param_uart2_rtscts (bool)
	Enable RTS and CTS pins
	Optional
	Default: 0
	Set to 1 to enable CTS and RTS pins

### uart3

Activates serial port 3 (/dev/ttyS3)

UART 3 pins (TX, RX): PD0, PD1

### uart4

Activates serial port 4 (/dev/ttyS4)

UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5

Parameters:

param_uart2_rtscts (bool)
	Enable RTS and CTS pins
	Optional
	Default: 0
	Set to 1 to enable CTS and RTS pins

### w1-gpio

Activates 1-Wire GPIO master
Requires external pull-up resistor on data pin

Parameters:

param_w1_pin (pin)
	Data pin for 1-Wire master
	Optional
	Default: PD4

param_w1_pin_int_pullup (bool)
	Enable internal pull-up for the data pin
	Optional
	Default: 0
	Set to 1 to enable the pull-up
	This option should not be used with multiple devices, parasite power setup
		or long wires -	please use external pull-up resistor instead