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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 616

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 226

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 857 227

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 738 178

Repositories

Showing 10 of 109 repositories
  • rocket-chip Public

    Rocket Chip Generator

    Scala 3,372 1,151 237 64 Updated Mar 7, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    SystemVerilog 83 Apache-2.0 45 86 13 Updated Mar 7, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4,185 Apache-2.0 616 323 (1 issue needs help) 157 Updated Mar 7, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    Rust 9 Apache-2.0 2 12 3 Updated Mar 7, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    Rust 104 Apache-2.0 51 116 50 Updated Mar 7, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    264 Apache-2.0 39 37 8 Updated Mar 7, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    SystemVerilog 12 Apache-2.0 8 32 4 Updated Mar 7, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ 35 LGPL-3.0 646 0 0 Updated Mar 7, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    SystemVerilog 308 ISC 75 47 (5 issues need help) 32 Updated Mar 7, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    SystemVerilog 266 Apache-2.0 79 19 0 Updated Mar 7, 2025

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