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@epfl-vlsc

EPFL VLSC

http://vlsc.epfl.ch/

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  1. parendi Public

    Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU

    C++ 19

  2. parendi-paperspace-demo Public

    Parendi's demo on Paperspace IPUs

    SystemVerilog

  3. memoro Public

    Memoro: A Detailed Heap Profiler

    CSS 181 16

  4. bitfiltrator Public

    Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

    Python 33 5

Repositories

Showing 10 of 25 repositories
  • rocketchip_fork Public

    A fork of rocket chip for Parendi

    Scala 0 0 0 0 Updated Apr 12, 2024
  • parendi Public

    Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU

    C++ 19 LGPL-3.0 0 0 1 Updated Apr 5, 2024
  • parendi-paperspace-demo Public

    Parendi's demo on Paperspace IPUs

    SystemVerilog 0 0 0 0 Updated Feb 15, 2024
  • chipyard_fork Public
    C 0 BSD-3-Clause 0 0 0 Updated Nov 28, 2023
  • yosys Public Forked from YosysHQ/yosys

    Yosys Open SYnthesis Suite

    C++ 0 ISC 925 0 0 Updated Sep 15, 2023
  • bitfiltrator Public

    Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

    Python 33 MIT 5 0 0 Updated Apr 8, 2023
  • memoro Public

    Memoro: A Detailed Heap Profiler

    CSS 181 MIT 16 2 7 Updated Dec 7, 2022
  • RapidWright Public Forked from Xilinx/RapidWright

    Build Customized FPGA Implementations for Vivado

    Java 0 114 0 0 Updated Oct 3, 2021
  • NvmFlow Public

    llvm based dataflow

    C++ 0 0 0 0 Updated Apr 27, 2021
  • incllnvm Public
    C++ 0 0 0 0 Updated Oct 23, 2020
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