A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

The AWS Serverless Application Model (AWS SAM) transform is a AWS CloudFormation macro that transforms SAM templates into CloudFormation templates.

The Most Comprehensive Survey of Video Quality Assessment to Date.

Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5

A suite of representative serverless cloud-agnostic (i.e., dockerized) benchmarks

Framework that integrates the serverless benchmark suite vSwarm with gem5, the state-of-the-art research platform for system-and microarchitecture.

隐蔽信道（Convert Channel）是MAC下的一种非法通信方式，可以使信息从高等级用户流向低等级用户，从而间接违背BLP模型中“不可上读，不可下写”的安全要求。

To realize algorithm using Python when studying bioinformatics principle

Reload+Refresh PoC

AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks

📚 计算机体系结构与C++书籍收集(持续更新)

Implementation of Utility based cache partitioning research paper in Champsim simulator

DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.

champsim simulation of Utility Based Cache dynamic partitioning (UCP).

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

Gem5 L2 Cache Partitioning

This repository contains the copy of GEM5 and aims to extend the simulator with way-based cache partitioning

RISC-V_QEMU_FULL-SYSTEM_GEM5-RTL_FRAMEWORK_EMULATION

Verilator open-source SystemVerilog simulator and lint system

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)

Template for projects using the Hwacha data-parallel accelerator