PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small, light weight, RISC CPU soft core

🌱 Open source ecosystem for open FPGA boards

A simple, basic, formally verified UART controller

A full-speed device-side USB peripheral core written in Verilog.

Fearless hardware design

Support files for participating in a Fomu workshop

A low pin count sniffer for ICEStick - targeting TPM chips

Implementation Nintendo's GameBoy console on an FPGA

A small 6502 system with MS BASIC in ROM

Experiments with Yosys cxxrtl backend

SDRAM controller with multiple wishbone slave ports

CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys

Misc iCE40 specific cores

A collection of yosys test cases I found useful to document