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Optimize dependence analysis in standard to handshake.
Handshake
#69
opened Aug 17, 2020 by
stephenneuendorffer
updated Aug 17, 2020
Implement Affine-To-Handshake
Handshake
#70
opened Aug 17, 2020 by
stephenneuendorffer
updated Aug 19, 2020
Handshake-runner should allow unbounded FIFOs
Handshake
#67
opened Aug 17, 2020 by
stephenneuendorffer
updated Aug 19, 2020
staticlogic needs a 'register' operation to pass control from one block to another.
StaticLogic
#122
opened Oct 5, 2020 by
stephenneuendorffer
updated Oct 17, 2020
[Verilator] Enable RTL simulation debugging
enhancement
New feature or request
#239
opened Nov 12, 2020 by
teqdruid
updated Nov 12, 2020
[FIRRTL] Support for comments?
FIRRTL
Involving the `firrtl` dialect
#223
opened Nov 9, 2020 by
lattner
updated Nov 19, 2020
[RTL/SV] Move UnpackedArrayType to SV dialect
#389
opened Jan 2, 2021 by
lattner
updated Jan 2, 2021
Cache non-inout bits in composite RTL types
#391
opened Jan 4, 2021 by
darthscsi
updated Jan 4, 2021
[ExportVerilog] Emit integer signedness in type
enhancement
New feature or request
HW
Involving the `hw` dialect
#397
opened Jan 5, 2021 by
teqdruid
updated Jan 5, 2021
[ExportVerilog] Should emit unsigned/signed for IntegerTypes which are not signless
#469
opened Jan 17, 2021 by
teqdruid
updated Jan 18, 2021
Add flag for SV v.s. V emission
enhancement
New feature or request
Verilog/SystemVerilog
Involving a Verilog dialect
#512
opened Jan 26, 2021 by
darthscsi
updated Jan 29, 2021
Lower bi-directional bundles to interfaces
enhancement
New feature or request
FIRRTL
Involving the `firrtl` dialect
#536
opened Jan 29, 2021 by
mikeurbach
updated Feb 18, 2021
[SV] Expose memory control signals for interfacing
#623
opened Feb 19, 2021 by
JuanEsco063
updated Feb 22, 2021
Standard-To-Handshake + handshake runner doesn't handle toplevel memories well.
Handshake
#68
opened Aug 17, 2020 by
stephenneuendorffer
updated Mar 3, 2021
CMake 3.20.0 triggers warnings concerning policies CMP0115 and CMP0116
#849
opened Mar 30, 2021 by
fabianschuiki
updated Mar 30, 2021
Add integration test cases for comparison const folding
FIRRTL
Involving the `firrtl` dialect
#852
opened Mar 30, 2021 by
fabianschuiki
updated Mar 30, 2021
--top isn't respected in driver.cpp for circt-rtl-sim.py
#896
opened Apr 7, 2021 by
darthscsi
updated Apr 7, 2021
[Handshake] New Handshake lowerings to target RTL/ESI/Comb/Seq dialects
enhancement
New feature or request
Handshake
#742
opened Mar 9, 2021 by
mikeurbach
updated Apr 10, 2021
[Python] 'Connect' syntax for Python bindings
enhancement
New feature or request
Python
Python bindings
#905
opened Apr 8, 2021 by
teqdruid
updated Apr 13, 2021
[exportverilog] Improve location options
ExportVerilog
#899
opened Apr 8, 2021 by
lattner
updated Apr 13, 2021
Ensure dialect dependencies are captured in ODS
#927
opened Apr 17, 2021 by
youngar
updated Apr 17, 2021
Hierarchy Viewer Pass/Tool
enhancement
New feature or request
#911
opened Apr 12, 2021 by
seldridge
updated Apr 17, 2021
[Python] Use type hints everywhere possible
Python
Python bindings
#1005
opened May 5, 2021 by
teqdruid
updated May 5, 2021
[LLHD] Flesh out zero-delay semantics
LLHD
#1010
opened May 5, 2021 by
fabianschuiki
updated May 5, 2021
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