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Pull requests: llvm/circt

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Pull requests list

[HWToLLVM][Arc] Add out-of-bounds handler for array accesses Arc Involving the `arc` dialect
#6956 opened Apr 26, 2024 by fzi-hielscher Loading…
1
5
[HW] Rework InnerSym infra to support nested symbol tables
#6933 opened Apr 19, 2024 by mortbopet Loading…
83
[FIRRTL] Add debug logging to dedup
#6916 opened Apr 12, 2024 by jackkoenig Loading…
14
[FIRRTL] Use lower-sigs to handle port scalarization of internal modules. This removes Lower Types from dealing with it in anticipation of Lower Types being simplified.
#6904 opened Apr 8, 2024 by darthscsi • Draft
1
[InferReadWrite] Update the heuristic to infer the enable signal
#6862 opened Mar 21, 2024 by prithayan Loading…
1
[Seq] Enforce non-negative preset values in FirRegOp printer/parser
#6856 opened Mar 20, 2024 by fzi-hielscher Loading…
4
[Arc] Add basic support for assert operation.
#6839 opened Mar 17, 2024 by elhewaty Loading…
2 tasks
1
54
[CheckCombLoops] Handle RWProbeOp
#6824 opened Mar 13, 2024 by prithayan Loading…
1
7
Add test_en port to EICG in extract instances unit tests
#6655 opened Feb 7, 2024 by mwachs5 Loading…
17
[LinkModules] Add support to link hw modules
#6619 opened Jan 29, 2024 by prithayan Loading…
26
[CombFolds] Revive Interval Canonicalization
#6607 opened Jan 25, 2024 by uenoku Loading…
2
[FIRRTL] Standalone initialization checking pass
#6598 opened Jan 22, 2024 by darthscsi Loading…
22
[FirRegLowering] Add a limit to nested-if depth
#6528 opened Dec 18, 2023 by uenoku Loading…
2
[CHIRRTL] Add a connect op
#6526 opened Dec 14, 2023 by darthscsi Loading…
1
[NFCI] Build windows CI with relwithdebinfo to see stack traces.
#6525 opened Dec 14, 2023 by darthscsi Loading…
4
[FirRegLowering] Reimplement forward slice analysis with SCC
#6490 opened Dec 5, 2023 by prithayan Loading…
18
[FIRRTL][ExpandWhens] Allow zero-width wires to be uninitialized
#6455 opened Nov 28, 2023 by albertchen-sifive Loading…
17
[FIRRTL] Add lowering option to inline memory wrapper modules (#5681)
#6450 opened Nov 27, 2023 by sterin Loading…
28
[FIRRTL] Mux reduction
#6410 opened Nov 10, 2023 by darthscsi Loading…
4
Replace waiver comments with a new waiver attribute
#6383 opened Nov 6, 2023 by prithayan Loading…
12
[FIRRTL] Implement intrinsic module pla
#6381 opened Nov 6, 2023 by SpriteOvO • Draft
5
[FIRRTL] Extend vector ops with a few more and unify naming.
#6295 opened Oct 16, 2023 by darthscsi • Draft
15
[HW][NFCI] Prevent null attributes in per_port_attrs array
#6257 opened Oct 5, 2023 by fzi-hielscher Loading…
5
Move getWidthOrSentinel to a new trait. This trait is exclusively for types which are purely physical.
#5989 opened Aug 29, 2023 by darthscsi Loading…
[ExportVerilog] Don't spill temporary for inout ports
#5981 opened Aug 29, 2023 by uenoku Loading…
3
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